PLLs in Stratix II and Stratix II GX Devices
Table 1–8. Fast PLL Input Signals (Part 2 of 2)
Name
pllena
Description
Source
Destination
Enable pin for enabling or disabling all or a set Pin
of PLLs. Active high.
PLL control signal
Switch-over signal used to initiate external clock Logic array
switch-over control. Active high.
Reconfiguration circuit
PLL control signal
PFD
clkswitch
areset
Enables the up/down outputs from the
phase-frequency detector. Active high.
Logic array
Enables the up/down outputs from the
phase-frequency detector. Active high.
Logic array
pfdena
Serial clock signal for the real-time PLL control Logic array
feature.
Reconfiguration circuit
Reconfiguration circuit
Reconfiguration circuit
Reconfiguration circuit
scanclk
scandata
scanwrite
scanread
Serial input data stream for the real-time PLL
control feature.
Logic array
Enables writing the data in the scan chain into Logic array
the PLL Active high.
Enables scan data to be written into the scan
chain Active high.
Logic array
Table 1–9. Fast PLL Output Signals
Name
Description
Source
Destination
PLL outputs driving regional or global clock.
PLL counter
Internal clock
c[3..0]
locked
Lock or gated lock output from lock detect circuit. Active
high.
PLL lock detect Logic array
Output of the last shift register in the scan chain.
PLL scan chain Logic array
PLL scan chain Logic array
scandataout
scandone
Signal indicating when the PLL has completed
reconfiguration. 1 to 0 transition indicates the PLL has
been reconfigured.
Altera Corporation
July 2009
1–17
Stratix II Device Handbook, Volume 2
ALTERA [ ALTERA CORPORATION ]
