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A16450 参数 Datasheet PDF下载

A16450图片预览
型号: A16450
PDF下载: 下载PDF文件 查看货源
内容描述: 通用异步接收器/发送器 [Universal Asynchronous Receiver/Transmitter]
分类和应用: 微控制器和处理器串行IO控制器通信控制器外围集成电路LTE时钟
文件页数/大小: 16 页 / 275 K
品牌: ALTERA [ ALTERA CORPORATION ]
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a16450 Universal Asynchronous Receiver/Transmitter Data Sheet  
Table 3. Interrupt Enable Register Format  
Bit Signal  
Description  
0
rda  
Received data available. When set to a logic high, bit 0 enables  
interrupts when receive data is loaded in the receiver buffer  
register.  
1
2
thre Transmitter holding register empty. When set to a logic high, bit 1  
enables interrupts when the transmitter holding register is empty.  
rls  
ms  
Receiver line status. When set to a logic high, bit 2 enables  
interrupts when the receiver line status register changes state.  
3
Modem status. When set to a logic high, bit 3 enables interrupts  
when the modem status register changes state.  
7..4  
Read-only bits that are always set to a logic low.  
Interrupt Identification Register  
The a16450has a priority encoding scheme for its four interrupt sources.  
Table 4 shows the encoding scheme for each of the interrupts, their  
priority, and the reset mechanism for each interrupt source. When set to a  
logic low, bit 0 indicates that an interrupt is pending. Bits 1 and 2 indicate  
the interrupt priority, and bits 3 through 7 are read-only bits that are  
always set to a logic low.  
Clearing an interrupt source does not affect any lower priority interrupts  
that might be pending. When the interrupt identification register is  
accessed, the highest priority interrupt at the beginning of the access is  
recorded in the register. Other interrupts, including those of higher  
priority, are recorded but are not recognized until the current register  
access is complete.  
Altera Corporation  
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