a16450 Universal Asynchronous Receiver/Transmitter Data Sheet
Table 4. Interrupt Identification Register Format
Note (1)
Bit 0
Bit 1
Bit 2 Bits 7..3 Interrupt Type Interrupt Source
Reset Mechanism Priority
1
0
X
1
X
1
0
0
No interrupt
–
–
–
Receiver line
status
Overrun, parity, or
Readthereceiverline Highest
framing errors; break status register
interrupt
0
0
0
1
1
0
0
0
Receiver data
available
Receiver data
available
Read the receiver
buffer
2
3
Transmitter
Transmitter holding Read the interrupt ID
holding register register empty
empty
register or write to the
transmitter holding
register
0
0
0
0
Modem status
cts, dsr, ri, or dcd Read the modem
change state status register
4
Note:
(1) The X indicates “don’t care.”
Line Control Register
The line control register sets the data and communication formats used by
the a16450. See Table 5.
72
Altera Corporation
ALTERA [ ALTERA CORPORATION ]
