a16450 Universal Asynchronous Receiver/Transmitter Data Sheet
Table 7 lists the number of stop bits and word length associated with bit 2.
Table 7. Stop Bit Control Format
Bit 2
Word Length
Note (1)
Number of Stop Bits
0
1
1
1
1
X
1
5 bits
6 bits
7 bits
8 bits
1.5
2
2
2
Note:
(1) The X indicates “don’t care.”
Modem Control Register
The modem control register controls the modem interface outputs.
Table 8 describes the modem control register format.
Table 8. Modem Control Register Format
Bit
Signal
Description
0
1
2
3
4
dtr
rts
Data terminal ready. The user can program the dtrbit to control the ndtroutput.
Request to send. The user can program the rtsbit to control the nrtsoutput.
out1 Output 1. The user can program the out1bit to control the nout1output.
out2 Output 2. The user can program the out2bit to control the nout2output.
el
Enable loopback. When high, bit 4 causes the following:
■ The soutoutput is set to a logic high.
■ The sininput is disconnected (i.e., ignored).
■ The output of the transmitter shift register is internally connected (loopbacked) to the
receiver shift register input.
■ The modem control inputs are disconnected (i.e., ignored).
■ The modem control outputs are used internally in place of the modem control inputs.
7..5
–
Not used. These read-only bits are always set to a logic low.
Line Status Register
The line status register enables the host processor to examine data
transfers. Table 9 describes the line status register format.
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