a16450 Universal Asynchronous Receiver/Transmitter Data Sheet
Table 5. Line Control Register Format
Bit
Description
1..0
Word length control. Sets the length of the word associated with each transmitted or received word.
See Table 6.
2
Stop control bit. Controls the number of stop bits generated by the transmitter section. The receiver
circuitry checks for the first stop bit only, regardless of the state of bit 2. See Table 7.
3
Parity enable. When set to a logic high, parity generation in the transmitter section and parity
checking in the receiver section are enabled. The parity bit is inserted between the last word bit and
the first stop bit.
4
5
Parity even/odd. When set to a logic high, even parity is enabled; when set to a logic low, odd parity
is enabled.
Stick parity. Forces the parity bit to a known value. If parity is enabled and even parity is selected, the
transmitter section will transmit the parity bit as a logic low. Then, the receiver section checks that the
incoming parity bit is set to logic low.
6
7
Break control. When set, bit 6 forces the a16450to transmit a break condition. The soutoutput is
forced to a logic low state for longer than one full word transmission. Disable the break by clearing
bit 6, which causes soutto return to a logic high. The soutoutput is set to a logic high upon master
reset.
Divisor register access bit (drab). This bit must be set high to access the divisor registers. A low
enables access to the receiver buffer and transmitter holding registers.
Table 6 lists the word length associated with bits 0 and 1.
Table 6. Word Length Control Format
Bit 0
Bit 1
Word Length
0
1
0
1
0
0
1
1
5 bits
6 bits
7 bits
8 bits
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