a16450 Universal Asynchronous Receiver/Transmitter Data Sheet
Register Address Map
The state of the a[2..0]inputs determines which internal register the
microprocessor addresses. See Table 2.
The divisor register access bit (drab) allows access to the divisor register.
The drabis bit 7 of the line control register.
Table 2. Register Address Map
drab (1)
a2
a1
a0
Register
0
0
0
0
Receiver buffer register—read only
Transmitter holding register—write only
1
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
1
1
0
1
0
1
0
1
Divisor register (LSB)
Interrupt enable register
Divisor register (MSB)
Interrupt ID register
Line control register
Modem control register
Line status register
1
X
X
X
X
X
X
Modem status register
Scratchpad register
Note:
(1) The X indicates “don’t care.”
Registers
The a16450MegaCore function contains the following registers:
■
■
■
■
■
■
■
■
■
■
Receiver buffer
Transmitter holding
Divisor
Interrupt enable
Interrupt identification
Line control
Modem control
Line status
Modem status
Scratchpad
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