2–26
Chapter 2: Device Datasheet for Cyclone V Devices
Configuration Specification
Configuration Specification
This section provides configuration specifications and timing for Cyclone V devices.
These characteristics can be designated as preliminary or final.
■
■
Preliminary characteristics are obtained using simulation results, process data,
and other known parameters. The title of these tables show the designation as
“Preliminary.”
Final numbers are based on actual silicon characterization and testing. The
numbers reflect the actual performance of the device under worst-case silicon
process, voltage, and junction temperature conditions. There are no designations
on finalized tables.
POR Specifications
Table 2–31 lists the specifications for fast and standard POR delay for Cyclone V
devices.
Table 2–31. Fast and Standard POR Delay Specification for Cyclone V Devices
POR Delay
Fast (1)
PORSEL Pin Setting
Minimum (ms)
Maximum (ms)
High
GND
4
12
Standard
100
300
Note to Table 2–31:
(1) The maximum pulse width of the fast POR delay is 12 ms, providing enough time for the PCIe hard IP to initialize
after the POR trip.
JTAG Configuration Timing
Table 2–32 lists the JTAG timing parameters and values for Cyclone V devices.
Table 2–32. JTAG Timing Parameters and Values for Cyclone V Devices—Preliminary
Symbol
Description
TCK clock period
Min
30
14
14
1
Max
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
tJCP
tJCH
tJCL
TCK clock high time
—
TCK clock low time
—
tJPSU (TDI)
tJPSU (TMS)
tJPH
TDI JTAG port setup time
TMS JTAG port setup time
JTAG port hold time
—
3
—
5
—
(1)
tJPCO
JTAG port clock to output
JTAG port high impedance to valid output
JTAG port valid output to high impedance
—
—
—
11
14
14
(1)
(1)
tJPZX
tJPXZ
Note to Table 2–32:
(1) A 1 ns adder is required for each VCCIO voltage step down from 3.0 V. For example, tJPCO = 12 ns if VCCIO of the TDO
I/O bank = 2.5 V, or 13 ns if it equals 1.8 V.
Cyclone V Device Handbook
Volume 1: Device Overview and Datasheet
February 2012 Altera Corporation
ALTERA [ ALTERA CORPORATION ]
