Chapter 2: Device Datasheet for Cyclone V Devices
2–25
Switching Characteristics
Table 2–29. OCT Calibration Block Specifications for Cyclone V Devices—Preliminary (Part 2 of 2)
Symbol
TOCTSHIFT
Description
Min
Typ
Max
Unit
Number of OCTUSRCLK clock cycles required for OCT code
to shift out
—
32
—
Cycles
Time required between the dyn_term_ctrland oesignal
transitions in a bidirectional I/O buffer to dynamically switch
between RS OCT and RT OCT
TRS_RT
—
2.5
—
ns
Figure 2–1 shows the timing diagram for the oeand dyn_term_ctrlsignals.
Figure 2–1. Timing Diagram for the oe and dyn_term_ctrl Signals
Tristate
Tristate
RX
TX
RX
oe
dyn_term_ctrl
TRS_RT
TRS_RT
[
Duty Cycle Distortion (DCD) Specifications
Table 2–30 lists the worst-case DCD for Cyclone V devices.
Table 2–30. Worst-Case DCD on I/O Pins for Cyclone V Devices—Preliminary
C6
C7, I7
Speed Grade
C8, A7
Speed Grade
Speed Grade
Symbol
Unit
Min
45
Max
Min
45
Max
Min
45
Max
Output Duty Cycle
55
55
55
%
February 2012 Altera Corporation
Cyclone V Device Handbook
Volume 1: Device Overview and Datasheet
ALTERA [ ALTERA CORPORATION ]
