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5CSEA2 参数 Datasheet PDF下载

5CSEA2图片预览
型号: 5CSEA2
PDF下载: 下载PDF文件 查看货源
内容描述: 旋风V器件手册 [Cyclone V Device Handbook]
分类和应用:
文件页数/大小: 74 页 / 1776 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Chapter 2: Device Datasheet for Cyclone V Devices  
Switching Characteristics  
2–23  
Unit  
Table 2–26. High-Speed I/O Specifications for Cyclone V Devices—Preliminary (2), (3) (Part 2 of 2)  
C6  
C7, I7  
Speed Grade  
C8, A7  
Speed Grade  
Speed Grade  
Symbol  
Conditions  
Min Typ  
Max Min Typ  
Max  
Min Typ  
Max  
TX output clock duty  
cycle for both True and  
Emulated Differential I/O  
Standards  
tDUTY  
45  
50  
55  
45  
50  
55  
45  
50  
55  
%
ps  
ps  
True Differential I/O  
Standards  
200  
250  
200  
250  
200  
300  
Emulated Differential I/O  
Standards with Three  
External Output Resistor  
Networks  
tRISE & tFALL  
Emulated Differential I/O  
Standards with One  
External Output Resistor  
Network  
300  
200  
300  
300  
250  
300  
300  
250  
300  
ps  
ps  
ps  
True Differential I/O  
Standards  
Emulated Differential I/O  
Standards with Three  
External Output Resistor  
Networks  
TCCS  
Emulated Differential I/O  
Standards with One  
External Output Resistor  
Network  
300  
300  
300  
ps  
Receiver  
(5)  
(5)  
(5)  
(5)  
(5)  
(5)  
SERDES factor J = 4 to 10  
875 (6)  
840 (6)  
640 (6) Mbps  
fHSDR (data rate)  
SERDES factor J = 1 to 2,  
Uses DDR Registers  
(7)  
(7)  
(7)  
Mbps  
Sampling Window  
350  
350  
350  
ps  
Notes to Table 2–26:  
(1) Pending silicon characterization.  
(2) When J = 1 or 2, bypass the serializer/deserializer (SERDES) block.  
(3) This is achieved by using the LVDS clock network.  
(4) Clock Boost Factor (W) is the ratio between the input data rate and the input clock rate.  
(5) The minimum specification depends on the clock source (for example, the PLL and clock pin) and the clock routing resource (global, regional,  
or local) that you use. The I/O differential buffer and input register do not have a minimum toggle rate.  
(6) You must calculate the leftover timing margin in the receiver by performing link timing closure analysis. You must consider the board skew  
margin, transmitter channel-to-channel skew, and receiver sampling margin to determine the leftover timing margin.  
(7) The maximum ideal frequency is the SERDES factor (J) x PLL max output frequency (fout), provided you can close the design timing and the  
signal integrity simulation is clean.You can estimate the achievable maximum data rate by performing link timing closure analysis. You must  
consider the board skew margin, transmitter delay margin, and receiver sampling margin to determine the maximum data rate supported.  
February 2012 Altera Corporation  
Cyclone V Device Handbook  
Volume 1: Device Overview and Datasheet  
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