1–10
Chapter 1: Overview for Cyclone V Device Family
Low-Power Serial Transceivers
Table 1–9. PCS Features of the Transceivers in Cyclone V Devices (Part 2 of 2)
PCS Support
Data Rates (Gbps)
Transmitter Datapath
■ Dedicated XAUI PHY IP core
■ XAUI synchronization state
Receiver Datapath
■ Dedicated XAUI PHY IP core
■ XAUI synchronization state
XAUI
3.125
machine for bonding four channels
machine for realigning four
channels
■ Custom PHY IP core with preset
■ Custom PHY IP core with preset
feature
feature
SRIO 1.3 and 2.1
1.25 to 3.125
■ SRIO version 2.1-compliant x2
■ SRIO version 2.1-compliant x2
and x4 channel bonding
and x4 deskew state machine
SDI, SD/HD, and
3G-SDI
0.27 (2), 1.485, and ■ Custom PHY IP core with preset
■ Custom PHY IP core with preset
2.97
feature
feature
■ Custom PHY IP core with preset
■ Custom PHY IP core with preset
feature
feature
Serial ATA Gen1 and
Gen2
1.5 and 3.0
■ Electrical idle
■ Signal detect
■ Wider spread of asynchronous
SSC
■ Dedicated deterministic latency
■ Dedicated deterministic latency
PHY IP core
PHY IP core
CPRI 4.1 (3)
OBSAI RP3
0.6144 to 4.9152
0.768 to 3.072
■ Transmitter (TX) manual bit-slip
■ Receiver (RX) deterministic
mode
latency state machine
■ Dedicated deterministic latency
■ Dedicated deterministic latency
PHY IP core
PHY IP core
■ TX manual bit-slip mode
■ RX deterministic latency state
machine
■ Custom PHY IP core
V-by-One HS
Up to 3.75
Custom PHY IP core
■ Wider spread of asynchronous
SSC
■ Custom PHY IP core
DisplayPort 1.2 (4)
1.62 and 2.7
Custom PHY IP core
■ Wider spread of asynchronous
SSC
■ Dedicated XAUI PHY IP core
■ Dedicated XAUI PHY IP core
■ XAUI synchronization state
■ XAUI synchronization state
machine for realigning four
channels
HiGig
3.75
machine for bonding four channels
Custom PHY IP core with preset
feature
Custom PHY IP core with preset
feature
JESD204A
0.3125 (2) to 3.125
Notes to Table 1–9:
(1) PCIe Gen2 is supported only for Cyclone V GT devices.
(2) The 0.27-Gbps and 0.3125-Gbps data rates are supported using oversampling user logic that you must implement in the FPGA fabric.
(3) High-voltage output mode (1000-BASE-CX) is not supported.
(4) Pending characterization.
Cyclone V Device Handbook
February 2012 Altera Corporation
Volume 1: Device Overview and Datasheet
ALTERA [ ALTERA CORPORATION ]
