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5CSEA2 参数 Datasheet PDF下载

5CSEA2图片预览
型号: 5CSEA2
PDF下载: 下载PDF文件 查看货源
内容描述: 旋风V器件手册 [Cyclone V Device Handbook]
分类和应用:
文件页数/大小: 74 页 / 1776 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Chapter 1: Overview for Cyclone V Device Family  
1–11  
PCIe Gen1 and Gen2 Hard IP  
PCIe Gen1 and Gen2 Hard IP  
Cyclone V GX, GT, SX, and ST devices contain PCIe hard IP—consisting of the MAC,  
data link, and transaction layers—that is designed for performance, ease-of-use, and  
increased functionality. The PCIe hard IP supports PCIe Gen2 end point and root port  
for x1 and x2 lanes configuration, and Gen1 end point and root port for up to x4 lane  
configuration.  
The PCIe endpoint support includes multifunction support for up to eight functions,  
as shown in Figure 1–2. The integrated multifunction support reduces the FPGA logic  
requirements by up to 20 K LEs for PCIe designs that require multiple peripherals.  
Figure 1–2. PCIe Multifunction for Cyclone V Devices  
External System  
Cyclone V Device  
Host CPU  
PCIe Link  
Root  
Complex  
Local  
Peripheral 1  
Local  
Peripheral 2  
The Cyclone V PCIe hard IP operates independently from the core logic. This  
independent operation allows the PCIe link to wake up and complete link training in  
less than 100 ms while the Cyclone V device completes loading the programming file  
for the rest of the device. In addition, the PCIe hard IP in the Cyclone V device  
provides improved end-to-end datapath protection using ECC.  
FPGA GPIOs  
Cyclone V devices offer highly configurable GPIOs. The following list describes the  
many features of the GPIOs:  
Programmable bus hold and weak pull-up.  
LVDS output buffer with programmable differential output voltage (VOD) and  
programmable pre-emphasis.  
Dynamic on-chip parallel termination (RT OCT) for all I/O banks with OCT  
calibration to limit the termination impedance variation to 15%.  
On-chip dynamic termination that has the ability to swap between serial and  
parallel termination, depending on whether there is read or write on a common  
bus for signal integrity.  
Unused voltage reference (VREF) pins that can be configured as user I/Os.  
Easy timing closure support using the hard read FIFO in the input register path,  
and delay-locked loop (DLL) delay chain with fine and coarse architecture.  
February 2012 Altera Corporation  
Cyclone V Device Handbook  
Volume 1: Device Overview and Datasheet  
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