1–8
Chapter 1: Overview for Cyclone V Device Family
Low-Power Serial Transceivers
Low-Power Serial Transceivers
Cyclone V devices deliver the industry’s lowest power 5-Gbps transceivers at an
estimated 88 mW maximum power consumption per channel. Cyclone V transceivers
are designed to be compliant for a wide range of protocols and data rates. The
transceivers are positioned on the left outer edge of the device, as shown in
Figure 1–1. The transceiver channels consist of the physical medium attachment
(PMA), physical coding sublayer (PCS), and clock networks.
Figure 1–1. Device Chip Overview for Cyclone V GX and GT Devices (1)
I/O, LVDS, and Memory Interface
Hard Memory Controller
Transceiver
PMA
Hard
PCS
Transceiver
PMA
Hard
PCS
Transceiver
PMA
Hard
PCS
Transceiver
Individual Channels
Distributed Memory
Core Logic Fabric and MLABs
M10K Internal Memory Blocks
Variable-Precision DSP Blocks
Hard Memory Controller
I/O, LVDS, and Memory Interface
Note to Figure 1–1:
(1) This figure represents a Cyclone V device with transceivers. Other Cyclone V devices may have a different floor plan than the one shown here.
Cyclone V Device Handbook
February 2012 Altera Corporation
Volume 1: Device Overview and Datasheet
ALTERA [ ALTERA CORPORATION ]
