Chapter 1: Overview for Cyclone V Device Family
1–9
Low-Power Serial Transceivers
PMA Support
To prevent core and I/O noise from coupling into the transceivers, the PMA block is
isolated from the rest of the chip—ensuring optimal signal integrity. For the
transceivers, you can use the channel PLL of an unused receiver PMA as an additional
transmit PLL.
Table 1–8 lists the PMA features of the transceiver.
Table 1–8. PMA Features of the Transceivers in Cyclone V Devices
Features
Capability
Up to 16” FR4 PCB fabric drive capability at up to 5 Gbps
Superior jitter tolerance
Backplane support
PLL-based clock recovery
Programmable deserialization and word alignment Flexible deserialization width and configurable word alignment pattern
Up to 6 dB of pre-emphasis, up to 4 dB of equalization, and no
Equalization and pre-emphasis
decision feedback equalizer (DFE)
Ring oscillator transmit PLLs
Input reference clock range
614 Mbps to 5 Gbps
20 MHz to 400 MHz
Allows the reconfiguration of a single channel without affecting the
operation of other channels
Transceiver dynamic reconfiguration
PCS Support
The Cyclone V core logic connects to the PCS through an 8-, 10-, 16-, 20-, 32-, or 40-bit
interface, depending on the transceiver data rate and protocol. Cyclone V devices
contain PCS hard IP to support PCIe Gen1 and Gen2, XAUI, Gbps Ethernet (GbE),
Serial RapidIO® (SRIO), and Common Public Radio Interface (CPRI). Most of the
other standard and proprietary protocols from 614 Mbps to 5.0 Gbps are supported.
Table 1–9 lists the PCS features of the transceiver.
Table 1–9. PCS Features of the Transceivers in Cyclone V Devices (Part 1 of 2)
PCS Support
Data Rates (Gbps)
Transmitter Datapath
■ Phase compensation FIFO
■ Byte serializer
Receiver Datapath
■ Word aligner
■ Deskew FIFO
■ 8B/10B encoder
■ Rate-match FIFO
■ 8B/10B decoder
■ Byte deserializer
■ Byte ordering
3-Gbps and 5-Gbps
Basic
■ Transmitter bit-slip
0.614 to 5.0
■ Receiver phase compensation
FIFO
■ Dedicated PCIe PHY IP core
■ Dedicated PCIe PHY IP core
PCIe Gen1: x1, x2, x4
PCIe Gen2: x1, x2 (1)
2.5 and 5.0
1.25
■ PIPE 2.0 interface to the core logic ■ PIPE 2.0 interface to the core logic
■ Custom PHY IP core with preset
■ Custom PHY IP core with preset
feature
feature
GbE
■ GbE transmitter synchronization
■ GbE receiver synchronization state
state machine
machine
February 2012 Altera Corporation
Cyclone V Device Handbook
Volume 1: Device Overview and Datasheet
ALTERA [ ALTERA CORPORATION ]
