5CSEA2 参数 Datasheet PDF下载

型号：	5CSEA2
PDF下载：	下载PDF文件查看货源
内容描述：	旋风V器件手册 [Cyclone V Device Handbook]
分类和应用：
文件页数/大小：	74 页 / 1776 K
品牌：	ALTERA [ ALTERA CORPORATION ]

1–6

Chapter 1: Overview for Cyclone V Device Family

Cyclone V Family Plan

Table 1–5. Maximum Resource Counts for Cyclone V SX and ST Devices—Preliminary (Part 2 of 2)

Cyclone V SX Device

Cyclone V ST Device

Resource

PCIe Hard IP Block

5CSXC4

5CSXC5

5CSXC6

5CSTD5

5CSTD6

FPGA Memory Controller

HPS Memory Controller

ARM Cortex-A9 MPCore Processor

Note to Table 1–5:

Dual-core

(1) The maximum FPGA fractional PLLs listed include FPGA general purpose PLLs and transceiver PLLs.

Table 1–6 lists the Cyclone V E, GX, and GT package plan that shows the GPIO count,

the maximum number of transceivers available, and the vertical migration capability

for each device package and density.

Table 1–6. Package Plan for Cyclone V E, GX, and GT Devices—Preliminary ⁽¹⁾

F256 U324 U484 F484

F672

(27 mm)

F896

(31 mm)

F1152

(35 mm)

(17 mm) (15 mm) (19 mm) (23 mm)

Device

5CEA2

5CEA4

144

—

176

—

288

272

240

—

288

272

240

224

208

240

224

240

224

—

560

—

560

—

5CEA5

—

5CEA7

—

336

—

480

448

—

5CEA9

—

5CGXC3 ⁽²⁾

5CGXC4 ⁽²⁾

5CGXC5 ⁽²⁾

5CGXC7 ⁽²⁾

5CGXC9 ⁽²⁾

5CGTD5 ⁽³⁾

5CGTD7 ⁽³⁾

5CGTD9 ⁽³⁾

Notes to Table 1–6:

112

—

208

224

240

—

336

368

336

—

480

448

—

240

—

480

448

—

(1) The arrows indicate the package vertical migration capability. You can also migrate your design across device densities in the same packaging

option if the devices have the same dedicated pins, configuration pins, and power pins.

(2) The transceiver counts listed are for 3-Gbps transceivers.

(3) The transceiver counts listed are for 5-Gbps transceivers.

Cyclone V Device Handbook

February 2012 Altera Corporation

Volume 1: Device Overview and Datasheet

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