AV-51001
2013.05.06
16
Adaptive Logic Module
Adaptive Logic Module
Arria V devices use a 28 nm ALM as the basic building block of the logic fabric.
The ALM, as shown in following figure, uses an 8-input fracturable look-up table (LUT) with four dedicated
registers to help improve timing closure in register-rich designs and achieve an even higher design packing
capability than previous generations.
Figure 7: ALM for Arria V Devices
FPGA Device
Reg
1
2
Full
Adder
3
4
5
6
7
Reg
Adaptive
LUT
Reg
Reg
8
Full
Adder
You can configure up to 50% of the ALMs in the Arria V devices as distributed memory using MLABs.
Related Information
Embedded Memory Capacity in Arria V Devices on page 19
Lists the embedded memory capacity for each device.
Variable-Precision DSP Block
Arria V devices feature a variable-precision DSP block that supports these features:
• Configurable to support signal processing precisions ranging from 9 x 9, 18 x 18, 27 x 27, and 36 x 36
bits natively
• A 64-bit accumulator
• Double accumulator
• A hard preadder that is available in both 18- and 27-bit modes
• Cascaded output adders for efficient systolic finite impulse response (FIR) filters
• Dynamic coefficients
• 18-bit internal coefficient register banks
• Enhanced independent multiplier operation
• Efficient support for single-precision floating point arithmetic
• The inferability of all modes by the Quartus II design software
Arria V Device Overview
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