AV-51001
2013.05.06
13
Available Options
Available Options
Figure 5: Sample Ordering Code and Available Options for Arria V ST Devices—Preliminary
Transceiver Count
Embedded Hard IPs
Package Type
Maximum channels
M
:
Maximum 1 hard PCIe
controller and 2 hard
memory controllers
Maximum 2 hard PCIe
controllers and 3 hard
memory controllers
F
:
FineLine BGA (FBGA)
E
G
K
:
:
:
12
18
30
Operating Temperature
F
:
I
:
Industrial (TJ = -40° C to 100° C)
Family Signature
5A
ST
F
D5
K
3
F
40
I
3
N
5A : Arria V
Optional Suffix
Indicates specific device
options or shipment method
Family Variant
ST : SoC FPGA with 10-Gbps transceivers
FPGA Fabric
Speed Grade
N
: Lead-free packaging
Member Code
ES : Engineering sample
D3 : 350K logic elements
D5 : 462K logic elements
3 (fastest)
5
Transceiver
Speed Grade
Package Code
31 : 896 pins
35 : 1,152 pins
40 : 1,517 pins
3
: 10.3125 Gbps
Maximum Resources
Table 12: Maximum Resource Counts for Arria V ST Devices—Preliminary
Member Code
Resource
D3
D5
462
Logic Elements (LE) (K)
350
132,075
528,300
17,290
2,014
809
ALM
174,340
697,360
22,820
2,658
1,090
2,180
14
Register
M10K
MLAB
Memory (Kb)
Variable-precision DSP Block
18 x 18 Multiplier
FPGA PLL14
1,618
14
HPS PLL
3
3
6-Gbps
10-Gbps15
30
30
Transceiver
16
16
14
The number of PLLs includes general-purpose fractional PLLs and transceiver fractional PLLs.
Chip-to-chip connections only. For 10 Gbps channel usage conditions, refer to the Transceiver Architecture
in Arria V Devices chapter. For information about 10 Gbps SFF-8431 compliance, contact Altera.
15
Arria V Device Overview
Altera Corporation
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