AV-51001
2013.05.06
12
Package Plan
Member Code
Resource
B3
B5
HPS PLL
3
3
6 Gbps Transceiver
FPGA GPIO13
HPS I/O
30
30
528
528
208
208
Transmitter
Receiver
121
121
LVDS
136
136
PCIe Hard IP Block
2
2
FPGA Hard Memory Controller
HPS Hard Memory Controller
3
1
3
1
ARM Cortex-A9 MPCore Processor
Dual-core
Dual-core
Related Information
High-Speed Differential I/O Interfaces and DPA in Arria V Devices chapter, Arria V Device Handbook
Provides the number of LVDS channels in each device package.
Package Plan
Table 11: Package Plan for Arria V SX Devices—Preliminary
F896
F1152
F1517
(31 mm)
(35 mm)
(40 mm)
Member
Code
FPGA
GPIO
HPS I/O
XCVR
FPGA
GPIO
HPS I/O
XCVR
FPGA
GPIO
HPS I/O
XCVR
B3
B5
170
170
208
208
12
12
350
350
208
208
18
18
528
528
208
208
30
30
Arria V ST
This section provides the available options, maximum resource counts, and package plan for the Arria V ST
devices.
13
The number of GPIOs does not include transceiver I/Os. In the Quartus II software, the number of user I/Os
includes transceiver I/Os.
Arria V Device Overview
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