AV-51001
2013.05.06
20
Embedded Memory Configurations
Embedded Memory Configurations
Table 17: Supported Embedded Memory Block Configurations for Arria V Devices
This table lists the maximum configurations supported for the embedded memory blocks. The information is
applicable only to the single-port RAM and ROM modes.
Memory Block
Depth (bits)
Programmable Width
32
x16, x18, or x20
MLAB
6417
512
1K
x10
x40
x20
2K
x10
M20K
M10K
4K
x5
8K
x2
16K
256
512
1K
x1
x40 or x32
x20 or x16
x10 or x8
x5 or x4
x2
2K
4K
8K
x1
Clock Networks and PLL Clock Sources
Arria V devices have 16 global clock networks capable of up to 650 MHz operation. The clock network
architecture is based on Altera's global, quadrant, and peripheral clock structure. This clock structure is
supported by dedicated clock input pins and fractional PLLs.
Note: To reduce power consumption, the Quartus II software identifies all unused sections of the clock
network and powers them down.
PLL Features
The PLLs in the Arria V devices support the following features:
• Frequency synthesis
• On-chip clock deskew
• Jitter attenuation
• Counter reconfiguration
• Programmable output clock duty cycles
• PLL cascading
17
Available for Arria V GZ devices only.
Arria V Device Overview
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