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5AGXMA3D631C4N 参数 Datasheet PDF下载

5AGXMA3D631C4N图片预览
型号: 5AGXMA3D631C4N
PDF下载: 下载PDF文件 查看货源
内容描述: 阿里亚V器件概述 [Arria V Device Overview]
分类和应用:
文件页数/大小: 37 页 / 793 K
品牌: ALTERA [ ALTERA CORPORATION ]
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AV-51001  
2013.05.06  
14  
Package Plan  
Member Code  
Resource  
D3  
D5  
FPGA GPIO16  
HPS I/O  
528  
540  
208  
210  
Transmitter  
Receiver  
121  
121  
LVDS  
136  
136  
PCIe Hard IP Block  
2
2
FPGA Hard Memory Controller  
HPS Hard Memory Controller  
3
1
3
1
ARM Cortex-A9 MPCore Processor  
Dual-core  
Dual-core  
Related Information  
High-Speed Differential I/O Interfaces and DPA in Arria V Devices chapter, Arria V Device Handbook  
Provides the number of LVDS channels in each device package.  
Transceiver Architecture in Arria V Devices  
Describes 10 Gbps channels usage conditions.  
Package Plan  
Table 13: Package Plan for Arria V ST DevicesPreliminary  
F896  
F1152  
F1517  
(31 mm)  
(35 mm)  
(40 mm)  
Mem-  
ber  
Code  
XCVR  
XCVR  
XCVR  
FPGA  
GPIO  
FPGA  
GPIO  
FPGA  
GPIO  
HPS I/O  
HPS I/O  
HPS I/O  
6 Gbps  
10  
6 Gbps  
10  
6 Gbps  
10  
Gbps  
Gbps  
Gbps  
D3  
D5  
170  
170  
208  
208  
12  
12  
6
6
350  
350  
208  
208  
18  
18  
8
8
528  
528  
208  
208  
30  
30  
16  
16  
16  
The number of GPIOs does not include transceiver I/Os. In the Quartus II software, the number of user I/Os  
includes transceiver I/Os.  
Arria V Device Overview  
Altera Corporation  
Feedback  
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