Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2017.12.15
Symbol
tPLL_PSERR
Parameter
Accuracy of PLL phase shift
Condition
Min
—
Typ
—
Max
±50
—
Unit
ps
—
—
—
tARESET
Minimum pulse width on areset signal.
10
—
—
ns
(32)
tCONFIGPLL
Time required to reconfigure scan chains for
PLLs
3.5
—
SCANCLK
cycles
fSCANCLK
—
—
—
100
MHz
scanclk frequency
Table 28.
PLL Specifications for Intel MAX 10 Single Supply Devices
For V36 package, the PLL specification is based on single supply devices.
Symbol
tOUTJITTER_PERIOD_DEDCLK
Parameter
Condition
Max
660
66
Unit
ps
(31)
Dedicated clock output period jitter
FOUT ≥ 100 MHz
FOUT < 100 MHz
FOUT ≥ 100 MHz
FOUT < 100 MHz
mUI
ps
(31)
tOUTJITTER_CCJ_DEDCLK
Dedicated clock output cycle-to-cycle jitter
660
66
mUI
Table 29.
PLL Specifications for Intel MAX 10 Dual Supply Devices
Symbol
tOUTJITTER_PERIOD_DEDCLK
Parameter
Condition
Max
300
30
Unit
ps
(31)
Dedicated clock output period jitter
FOUT ≥ 100 MHz
FOUT < 100 MHz
FOUT ≥ 100 MHz
FOUT < 100 MHz
mUI
ps
(31)
tOUTJITTER_CCJ_DEDCLK
Dedicated clock output cycle-to-cycle jitter
300
30
mUI
(32)
With 100 MHz scanclk frequency.
Intel® MAX® 10 FPGA Device Datasheet
28
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