September 2005
ASM5P23S08A
rev 1.4
Pin Configuration
REF
CLKA1
1
2
16
15
FBK
CLKA4
CLKA3
CLKA2
VDD
3
4
5
6
7
8
14
13
12
11
ASM5P23S08A
VDD
GND
GND
CLKB1
CLKB4
CLKB3
10
9
CLKB2
S2
S1
Pin Description for ASM5P23S08A
Pin #
Pin Name
Description
1
2
REF3
CLKA14
CLKA24
VDD
Input reference frequency, 5V tolerant input
Buffered clock output, bank A
Buffered clock output, bank A
3.3V supply
3
4
5
GND
Ground
6
CLKB14
CLKB24
S25
Buffered clock output, bank B
Buffered clock output, bank B
Select input, bit 2
7
8
9
S15
Select input, bit 1
10
11
12
13
14
15
16
CLKB34
CLKB44
GND
Buffered clock output, bank B
Buffered clock output, bank B
Ground
VDD
3.3V supply
CLKA34
CLKA44
FBK
Buffered clock output, bank A
Buffered clock output, bank A
PLL feedback input
Notes:
3. Weak pull-down.
4. Weak pull-down on all outputs.
5. Weak pull-up on these inputs.
3.3V ‘SpreadTrak’ Zero Delay Buffer
4 of 18
Notice: The information in this document is subject to change without notice.
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
