AS4LC4M16S0
AS4LC16M4S0
®
write interrupted by write (BL = 4)
CLK
CMD
ADD
DQ
t
CCD
Write data Write data
A
B
0
0
DB
DB
3
DA
DB
DB
1
2
0
0
t
CDL
t
t
= CAS to CAS delay (= 1 CLK)
= last address in to new column addres delay (= 1 CLK)
CCD
CDL
write interrupted by read (CL = 2, BL = 4)
CLK
t
CCD
CMD
ADD
Write data Read data
A
B
DQ (CL2)
DQ (CL3)
DA
QB
QB
QB
QB
3
0
0
1
2
DA
QB
QB
QB
QB
3
0
0
1
2
t
CDL
t
t
= CAS to CAS delay (= 1 CLK)
= last address in to new column addres delay (= 1 CLK)
CCD
CDL
read interrupted by write (CL = 3, BL = 4)
CLK
CMD
DQM
DQ
Read data
Write data*
Q
D
D
D
D
3
0
1
2
0
*
To prevent bus contention, maintain a gap between data in and data out.
Burst termination
Burst operations may be terminated with a Read, Write, Burst Stop, or Precharge command. When Burst Stop is asserted
during the read cycle, burst read data is terminated and the data bus goes to High Z after CAS latency. When Burst Stop is
asserted during the write cycle, burst write data is terminated and the databus goes to High Z simultaneously.
Burst stop command waveform, read cycle
(BL = 8)
CLK
CMD
Read data
Burst stop
DQ (CL = 2)
DQ (CL = 3)
Q
Q
Q
2
0
1
Q
Q
Q
2
0
1
16
ALLIANCE SEMICONDUCTOR
7/ 5/ 00
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
