欢迎访问ic37.com |
会员登录 免费注册
发布采购

AS4LC8M8S0-10TC 参数 Datasheet PDF下载

AS4LC8M8S0-10TC图片预览
型号: AS4LC8M8S0-10TC
PDF下载: 下载PDF文件 查看货源
内容描述: 3.3V 4Mx16和8Mx8 CMOS同步DRAM [3.3V 4Mx16 and 8Mx8 CMOS synchronous DRAM]
分类和应用: 动态存储器
文件页数/大小: 24 页 / 548 K
品牌: ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
 浏览型号AS4LC8M8S0-10TC的Datasheet PDF文件第8页浏览型号AS4LC8M8S0-10TC的Datasheet PDF文件第9页浏览型号AS4LC8M8S0-10TC的Datasheet PDF文件第10页浏览型号AS4LC8M8S0-10TC的Datasheet PDF文件第11页浏览型号AS4LC8M8S0-10TC的Datasheet PDF文件第13页浏览型号AS4LC8M8S0-10TC的Datasheet PDF文件第14页浏览型号AS4LC8M8S0-10TC的Datasheet PDF文件第15页浏览型号AS4LC8M8S0-10TC的Datasheet PDF文件第16页  
AS4LC4M16S0  
AS4LC16M4S0  
®
Mode register set command waveform  
CLK  
CMD  
ACT  
PRE  
MRS  
t
t
(min)  
RP  
RSC  
MRS can be issued only when both banks are idle.  
Precharge waveforms  
Precharge can be asserted after tRAS (min). The selected bank will enter the idle state after tRP.. The earliest assertion of the  
precharge command without losing any burst data is show below.  
(normal write; BL = 4)  
CLK  
CMD  
WE  
PRE  
DQ  
D
0
D
1
D
D
3
2
(normal read; BL = 4)  
CLK  
CMD  
Read data  
PRE  
DQ(CL2)  
DQ(CL3)  
Q
Q
Q
Q
3
0
1
2
Q
Q
Q
Q
3
0
1
2
Auto precharge waveforms  
A10 controls the selection of auto precharge during the read or write command cycle.  
(write with auto precharge; BL = 4)  
CLK  
CMD  
DQ  
WE  
D
0
D
D
D
3
1
2
Auto precharge starts*  
(read with auto precharge; BL = 4)  
CLK  
CMD  
Read data  
DQ(CL2)  
DQ(CL3)  
Q
Q
Q
Q
3
0
1
2
Q
Q
Q
Q
3
0
1
2
Auto precharge starts*  
The row active command of the precharge bank can be issued after t from this point. At burst read/ write with auto precharge, CAS interrupt of the same  
*
RP  
bank is illegal; other bank is described below.  
12  
ALLIANCE SEMICONDUCTOR  
7/ 5/ 00  
 复制成功!