欢迎访问ic37.com |
会员登录 免费注册
发布采购

AS4LC8M8S0-10TC 参数 Datasheet PDF下载

AS4LC8M8S0-10TC图片预览
型号: AS4LC8M8S0-10TC
PDF下载: 下载PDF文件 查看货源
内容描述: 3.3V 4Mx16和8Mx8 CMOS同步DRAM [3.3V 4Mx16 and 8Mx8 CMOS synchronous DRAM]
分类和应用: 动态存储器
文件页数/大小: 24 页 / 548 K
品牌: ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
 浏览型号AS4LC8M8S0-10TC的Datasheet PDF文件第13页浏览型号AS4LC8M8S0-10TC的Datasheet PDF文件第14页浏览型号AS4LC8M8S0-10TC的Datasheet PDF文件第15页浏览型号AS4LC8M8S0-10TC的Datasheet PDF文件第16页浏览型号AS4LC8M8S0-10TC的Datasheet PDF文件第18页浏览型号AS4LC8M8S0-10TC的Datasheet PDF文件第19页浏览型号AS4LC8M8S0-10TC的Datasheet PDF文件第20页浏览型号AS4LC8M8S0-10TC的Datasheet PDF文件第21页  
AS4LC8M8S0  
AS4LC4M16S0  
®
writecycle  
CLK  
CMD  
Write data  
Burst stop  
DQ  
(CL = 2,3)  
Q
Q
Q
Q
3
0
1
2
Precharge command  
A Precharge command can be used to interrupt burst read/ write operation during the read cycle. During RD, burst read is  
terminated and o/ p goes to High Z after CAS latency. The same bank can be activated after tRP. During write, burst write  
operation is terminated immediately. Data written two cycles prior to the precharge command will be correctly stored. Set  
DQM high one cycle before Precharge command and hold it high until Precharge command to mask and avoid writing invalid  
data.  
read cycle (CL = 2)  
CLK  
CMD  
Read data  
PRE  
ACT  
DQ  
Q
Q
Q
Q
0
1
2
3
t
RP  
read cycle (CL = 3)  
CLK  
CMD  
DQ  
Read data  
PRE  
Q1  
ACT  
Q0  
Q2  
Q3  
write cycle (BL = 8)  
CLK  
CMD  
DQ  
Write data  
PRE  
ACT  
D
Q
4
D
D
2
D
0
3
1
t
Masked  
RP  
DQM  
7/ 5/ 00  
ALLIANCE SEMICONDUCTOR  
17  
 复制成功!