AS4LC8M8S0
AS4LC4M16S0
®
writecycle
CLK
CMD
Write data
Burst stop
DQ
(CL = 2,3)
Q
Q
Q
Q
3
0
1
2
Precharge command
A Precharge command can be used to interrupt burst read/ write operation during the read cycle. During RD, burst read is
terminated and o/ p goes to High Z after CAS latency. The same bank can be activated after tRP. During write, burst write
operation is terminated immediately. Data written two cycles prior to the precharge command will be correctly stored. Set
DQM high one cycle before Precharge command and hold it high until Precharge command to mask and avoid writing invalid
data.
read cycle (CL = 2)
CLK
CMD
Read data
PRE
ACT
DQ
Q
Q
Q
Q
0
1
2
3
t
RP
read cycle (CL = 3)
CLK
CMD
DQ
Read data
PRE
Q1
ACT
Q0
Q2
Q3
write cycle (BL = 8)
CLK
CMD
DQ
Write data
PRE
ACT
D
Q
4
D
D
2
D
0
3
1
t
Masked
RP
DQM
7/ 5/ 00
ALLIANCE SEMICONDUCTOR
17