AS4C256M16D3
READ Operation
Read Burst Operation
During a READ or WRITE command DDR3 will support BC4 and BL8 on the fly using address A12 during the
READ or WRITE (AUTO PRECHARGE can be enabled or disabled).
A12=0, BC4 (BC4 = burst chop, tCCD=4)
A12=1, BL8
A12 will be used only for burst length control, not a column address.
Figure 16. READ Burst Operation RL=5 (AL=0, CL=5, BL=8)
T9
T10
NOP
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK#
CK
Notes 3
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
Notes 4
Bank,
Col n
ADDRESS
tRPRE
tRPST
DQS, DQS#
Notes 2
DQ
Dout
n
Dout
n+1
Dout
n+2
Dout
n+3
Dout
n+4
Dout
n+5
Dout
n+6
Dout
n+7
CL = 5
RL = AL + CL
NOTES:
1. BL8, RL = 5, AL = 0, CL = 5.
2. Dout n = data-out from column n.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BL8 setting activated by either MR0[A1:0 = 00] or MR0[A1:0 = 01] and A12 = 1 during READ command at T0.
TRANSITIONING DATA
Don't Care
Figure 17. READ Burst Operation RL=9 (AL=4, CL=5, BL=8)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
NOP
CK#
CK
Notes 3
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
Notes 4
Bank,
Col n
ADDRESS
tRPRE
DQS, DQS#
Notes 2
DQ
Dout
n
Dout
n+1
Dout
n+2
AL = 4
CL = 5
RL = AL + CL
NOTES:
1. BL8, RL = 9, AL = (CL-1), CL = 5.
2. Dout n = data-out from column n.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BL8 setting activated by either MR0[A1:0 = 00] or MR0[A1:0 = 01] and A12 = 1 during READ command at T0.
TRANSITIONING DATA
Don't Care
Confidential
41
Rev. 3.0
Aug. /2014
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
