AS4C256M16D3
DRAM setting for write leveling and DRAM termination function in that mode
DRAM enters into Write leveling mode if A7 in MR1 set “High” and after finishing leveling, DRAM exits from
write leveling mode if A7 in MR1 set “Low”. Note that in write leveling mode, only DQS/DQS# terminations are
activated and deactivated via ODT pin not like normal operation.
Table 21. DRAM termination function in the leveling mode
ODT pin at DRAM
DQS, DQS# termination
DQs termination
De-asserted
Asserted
off
on
off
off
Note 1:
In write leveling mode with its output buffer disabled (MR1[bit7]=1 with MR1[bit12]=1) all RTT_Nom settings are
allowed; in Write Leveling Mode with its output buffer enabled (MR1[bit7]=1 with MR1[bit12]=0) only RTT_Nom
settings of RZQ/2, RZQ/4, and RZQ/6 are allowed.
Procedure Description
Memory controller initiates Leveling mode of all DRAMs by setting bit 7 of MR1 to 1. With entering write leveling
mode, the DQ pins are in undefined driving mode. During write leveling mode, only NOP or Deselect commands
are allowed. As well as an MRS command to exit write leveling mode. Since the controller levels one rank at a
time, the output of other rank must be disabled by setting MR1 bit A12 to 1. Controller may assert ODT after
tMOD, time at which DRAM is ready to accept the ODT signal.
Controller may drive DQS low and DQS# high after a delay of tWLDQSEN, at which time DRAM has applied on-
die termination on these signals. After tDQSL and tWLMRD controller provides a single DQS, DQS# edge which
is used by the DRAM to sample CK – CK# driven from controller. tWLMRD(max) timing is controller dependent.
DRAM samples CK – CK# status with rising edge of DQS and provides feedback on all the DQ bits
asynchronously after tWLO timing. There is a DQ output uncertainty of tWLOE defined to allow mismatch on
DQ bits; there are no read strobes (DQS/DQS) needed for these DQs. Controller samples incoming DQ and
decides to increment or decrement DQS – DQS# delay setting and launches the next DQS/DQS# pulse after
some time, which is controller dependent. Once a 0 to 1 transition is detected, the controller locks DQS – DQS#
delay setting and write leveling is achieved for the device.
Figure14. Timing details of Write Leveling sequence
(DQS – DQS# is capturing CK – CK# low at T1 and CK – CK# high at T2)
T2
T1
tWLH
Notes 5
tWLS
tWLS
tWLH
CK#
CK
Notes 1
Notes 2
MRS
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
tMOD
ODT
Notes 6
Notes 6
Notes 6
Notes 6
tDQSH
tDQSH
tDQSL
tDQSL
Notes 4
tWLDQSEN
Diff_DQS
tWLMRD
tWLO
One Prime DQ:
Notes 3
tWLO
Prime DQ
tWLO
Late Remaining DQs
Early Remaining DQs
tWLO
tWLOE
All DQs are Prime:
Notes 3
tWLO
Late Prime DQs
tWLOE
tWLMRD
tWLO
Notes 3
tWLO
Early Prime DQs
tWLO
tWLOE
NOTES
1. MRS: Load MR1 to enter write leveling mode.
2. NOP: NOP or Deselect.
UNDEFINED Driving MODE TIME BREAK
Don't Care
3. DRAM has the option to drive leveling feedback on a prime DQ or all DQs. If feedback is driven only on one DQ, the remaining DQs must be driven low, as shown in above Figure,
and maintained at this state through out the leveling procedure.
4. diff_DQS is the differential data strobe (DQS, DQS#). Timing reference points are the zero crossings. DQS is shown with solid line, DQS# is shown with dotted line.
5. CK, CK# : CK is shown with solid dark line, where as CK# is drawn with dotted line.
6. DQS, DQS# needs to fulfill minimum pulse width requirements tDQSH(min) and tDQSL(min) as defined for regular Writes; the max pulse width is system dependent.
Confidential
38
Rev. 3.0
Aug. /2014
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
