AS4C256M16D3
Write Leveling
For better signal integrity, DDR3 memory adopted fly by topology for the commands, addresses, control signals,
and clocks. The fly by topology has benefits from reducing number of stubs and their length but in other aspect,
causes flight time skew between clock and strobe at every DRAM on DIMM. It makes it difficult for the Controller
to maintain tDQSS, tDSS, and tDSH specification. Therefore, the controller should support “write leveling” in
DDR3 SDRAM to compensate the skew.
The memory controller can use the “write leveling” feature and feedback from the DDR3 SDRAM to adjust the
DQS – DQS# to CK – CK# relationship. The memory controller involved in the leveling must have adjustable
delay setting on DQS – DQS# to align the rising edge of DQS – DQS# with that of the clock at the DRAM pin.
DRAM asynchronously feeds back CK – CK#, sampled with the rising edge of DQS – DQS#, through the DQ
bus. The controller repeatedly delays DQS – DQS# until a transition from 0 to 1 is detected. The DQS – DQS#
delay established though this exercise would ensure tDQSS specification.
Besides tDQSS, tDSS, and tDSH specification also needs to be fulfilled. One way to achieve this is to combine
the actual tDQSS in the application with an appropriate duty cycle and jitter on the DQS- DQS# signals.
Depending on the actual tDQSS in the application, the actual values for tDQSL and tDQSH may have to be
better than the absolute limits provided in “AC Timing Parameters” section in order to satisfy tDSS and tDSH
specification.
DQS/DQS# driven by the controller during leveling mode must be determined by the DRAM based on ranks
populated. Similarly, the DQ bus driven by the DRAM must also be terminated at the controller.
One or more data bits should carry the leveling feedback to the controller across the DRAM configurations X16.
On a X16 device, both byte lanes should be leveled independently. Therefore, a separate feedback mechanism
should be available for each byte lane. The upper data bits should provide the feedback of the upper diff_DQS
(diff_UDQS) to clock relationship whereas the lower data bits would indicate the lower diff_DQS (diff_LDQS) to
clock relationship.
Figure 13. Write Leveling Concept
T0
T1
T2
T3
T4
T5
T6
T7
CK#
CK
Source
Diff_DQS
Tn
T0
T1
T2
T3
T4
T5
T6
CK#
CK
Destination
Diff_DQS
DQ
0 or 1
0
0
0
Push DQS to capture
0-1 transition
Diff_DQS
DQ
0 or 1
1
1
1
Confidential
37
Rev. 3.0
Aug. /2014
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
