AS4C256M16D3
Table 16. IDD specification parameters and test conditions (V
DD = 1.5V 0.075V)
-12
BCN/BIN
Parameter & Test Condition
Symbol
Unit
Max.
Operating One Bank Active-Precharge Current
CKE: High; External clock: On; BL: 8*1; AL: 0; CS#: High between ACT and
PRE; Command, Address, Bank Address Inputs: partially toggling; Data IO:
MID-LEVEL; DM:stable at 0; Bank Activity: Cycling with one bank active at a
time: 0,0,1,1,2,2,...;Output Buffer and RTT: Enabled in Mode Registers*2;
ODT Signal: stable at 0.
IDD0
85
mA
Operating One Bank Active-Read-Precharge Current
CKE: High; External clock: On; BL: 8*1, 7; AL:0; CS#: High between ACT, RD
and PRE; Command, Address, Bank Address Inputs, Data IO: partially
toggling; DM:stable at 0; Bank Activity: Cycling with one bank active at a
time: 0,0,1,1,2,2,...; Output Buffer and RTT: Enabled in Mode Registers*2;
ODT Signal: stable at 0.
IDD1
110
mA
Precharge Standby Current
CKE: High; External clock: On; BL: 8*1; AL: 0; CS#: stable at 1; Command,
Address, Bank Address Inputs: partially toggling; Data IO: MID-LEVEL;
DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT:
Enabled in Mode Registers*2; ODT Signal: stable at 0.
IDD2N
50
18
mA
mA
Precharge Power-Down Current Slow Exit
CKE: Low; External clock: On; BL: 8*1; AL: 0; CS#: stable at 1; Command,
Address, Bank Address Inputs: stable at 0; Data IO: MID-LEVEL; DM:stable
at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in
Mode Registers*2; ODT Signal: stable at 0; Precharge Power Down Mode:
Slow Exit.*3
IDD2P0
Precharge Power-Down Current Fast Exit
CKE: Low; External clock: On; BL: 8*1; AL: 0; CS#: stable at 1; Command,
Address, Bank Address Inputs: stable at 0; Data IO: MID-LEVEL; DM:stable
at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in
Mode Registers*2; ODT Signal: stable at 0; Precharge Power Down Mode:
Fast Exit.*3
IDD2P1
37
mA
Precharge Quiet Standby Current
CKE: High; External clock: On; BL: 8*1; AL: 0; CS#: stable at 1; Command,
Address, Bank Address Inputs: stable at 0; Data IO: MID-LEVEL; DM:stable
at 0;Bank Activity: all banks closed; Output Buffer and RTT: Enabled in
Mode Registers*2; ODT Signal: stable at 0.
IDD2Q
IDD3N
IDD3P
50
70
45
mA
mA
mA
Active Standby Current
CKE: High; External clock: On; BL: 8*1; AL: 0; CS#: stable at 1; Command,
Address, Bank Address Inputs: partially toggling; Data IO: MID-LEVEL;
DM:stable at 0;Bank Activity: all banks open; Output Buffer and RTT:
Enabled in Mode Registers*2; ODT Signal: stable at 0.
Active Power-Down Current
CKE: Low; External clock: On; BL: 8*1; AL: 0; CS#: stable at 1; Command,
Address, Bank Address Inputs: stable at 0; Data IO: MID-LEVEL;DM:stable
at 0; Bank Activity: all banks open; Output Buffer and RTT: Enabled in
Mode Registers*2; ODT Signal: stable at 0
Operating Burst Read Current
CKE: High; External clock: On; BL: 8*1, 7; AL: 0; CS#: High between RD;
Command, Address, Bank Address Inputs: partially toggling; DM:stable at
0; Bank Activity: all banks open, RD commands cycling through banks:
0,0,1,1,2,2,...; tput Buffer and RTT: Enabled in Mode Registers*2; ODT
Signal: stable at 0.
IDD4R
280
225
mA
mA
Operating Burst Write Current
CKE: High; External clock: On; BL: 8*1; AL: 0; CS#: High between WR;
Command, Address, Bank Address Inputs: partially toggling; DM: stable at
0; Bank Activity: all banks open. Output Buffer and RTT: Enabled in Mode
Registers*2; ODT Signal: stable at HIGH.
IDD4W
Confidential
24
Rev. 3.0
Aug. /2014
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
