AS4C256M16D3
Table 14. Differential AC and DC Input Levels
Symbol
VIHdiff
Parameter
Differential input high
Min.
0.2
Max.
Note 3
Unit Note
V
V
V
V
1
1
2
2
VILdiff
Differential input logic low
Differential input high ac
Differential input low ac
Note 3
- 0.2
VIHdiff(ac)
VILdiff(ac)
2 x (VIH(ac) - VREF
)
Notes 3
Note 3
2 x (VIL(ac) - VREF
)
NOTE 1: Used to define a differential signal slew-rate.
NOTE 2: For CK - CK# use VIH/VIL(ac) of ADD/CMD and VREFCA; for DQSL, DQSL#, DQSU, DQSU# use VIH/VIL(ac)
of DQs and VREFDQ; if a reduced ac-high or ac-low level is used for a signal group, then the reduced level
applies also here.
NOTE 3: These values are not defined; however, the single-ended signals CK, CK#, DQSL, DQSL#, DQSU, DQSU# need
to be within the respective limits (VIH(dc) max, VIL(dc)min) for single-ended signals as well as the limitations for
overshoot and undershoot.
Table 15. Capacitance (VDD = 1.5V, f = 1MHz, TOPER = 25 C)
DDR3-1600
Symbol
CIO
Parameter
Unit Note
Min.
Max.
Input/output capacitance,
(DQ, DM, DQS, DQS#)
1, 2, 3
1.5
2.3
pF
2, 3
CCK
Input capacitance, CK and CK#
0.8
0
1.4
0.15
0.15
1.3
0.2
0.4
0.3
3
pF
Input capacitance delta,
CK and CK#
2, 3, 4
CDCK
pF
Input/output capacitance delta,
DQS and DQS#
2, 3, 5
CDDQS
CI
0
pF
Input capacitance,
(CTRL, ADD, CMD input-only pins)
2, 3, 6
0.75
-0.4
-0.4
-0.5
-
pF
Input capacitance delta,
(All CTRL input-only pins)
2, 3,
7, 8
CDI_CTRL
CDI_ADD_CMD
CDIO
pF
Input capacitance delta,
(All ADD, CMD input-only pins)
2, 3,
9, 10
pF
Input/output capacitance delta,
(DQ, DM, DQS, DQS#)
2, 3,
11
pF
2, 3,
12
CZQ
Input/output capacitance of ZQ pin
pF
NOTE 1: Although the DM pins have different functions, the loading matches DQ and DQS.
NOTE 2: This parameter is not subject to production test. It is verified by design and characterization. VDD=VDDQ=1.5V,
VBIAS=VDD/2 and on die termination off.
NOTE 3: This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here.
NOTE 4: Absolute value of CCK-CCK#.
NOTE 5: Absolute value of CIO(DQS)-CIO(DQS#).
NOTE 6: CI applies to ODT, CS#, CKE, A0-A14, BA0-BA2, RAS#, CAS#, WE#.
NOTE 7: CDI_CTRL applies to ODT, CS# and CKE.
NOTE 8: CDI_CTRL=CI(CTRL)-0.5*(CI(CK)+CI(CK#)).
NOTE 9: CDI_ADD_CMD applies to A0-A12, BA0-BA2, RAS#, CAS# and WE#.
NOTE 10: CDI_ADD_CMD=CI(ADD_CMD) - 0.5*(CI(CK)+CI(CK#)).
NOTE 11: CDIO=CIO(DQ,DM) - 0.5*(CIO(DQS)+CIO(DQS#)).
NOTE 12: Maximum external load capacitance on ZQ pin: 5 pF.
Confidential
23
Rev. 3.0
Aug. /2014
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
