AS4C256M16D3
4
-
-
-
Mode Register Set command cycle time
Mode Register Set command update delay
tMRD
tMOD
tCK
max
(12nCK,
15ns)
4
CAS# to CAS# command delay
tCCD
tCK
tCK
tCK
WR + tRP
Auto precharge write recovery + precharge time
Multi-Purpose Register Recovery Time
tDAL(min)
tMPRR
tRRD
tFAW
1
-
-
max (4nCK,
7.5ns)
ACTIVE to ACTIVE command period
Four activate window
40
45
-
-
-
ns
ps
ps
AC175
Command and Address setup time to CK,
CK# referenced to Vih(ac) / Vil(ac) levels
tIS(base)
170
AC150
DC100
Command and Address hold time from CK,
CK# referenced to Vih(dc) / Vil(dc) levels
Control and Address Input pulse width for
each input
120
560
-
-
tIH(base)
tIPW
ps
ps
512
256
64
-
-
-
Power-up and RESET calibration time
Normal operation Full calibration time
Normal operation Short calibration time
tZQinit
tZQoper
tZQCS
tCK
tCK
tCK
max (5nCK,
tRFC+ 10ns)
max (5nCK,
tRFC +10ns)
-
-
-
-
Exit Reset from CKE HIGH to a valid command
tXPR
Exit Self Refresh to commands not
requiring a locked DLL
Exit Self Refresh to commands requiring a
locked DLL
Minimum CKE low width for Self Refresh
entry to exit timing
tXS
tDLLK (min)
tXSDLL
tCKESR
tCK
tCKE (min) +
1 nCK
max
(5 nCK,
10ns)
max
(5 nCK,
10ns)
Valid Clock Requirement after Self Refresh Entry
(SRE) or Power-Down Entry (PDE)
-
-
tCKSRE
tCKSRX
tXP
Valid Clock Requirement before Self Refresh Exit
(SRX) or Power-Down Exit (PDX) or Reset Exit
Exit Power Down with DLL on to any valid command;
Exit Precharge Power Down with DLL frozen to
commands not requiring a locked DLL
max
(3 nCK,
6ns)
-
-
max
(10nCK,
24ns)
max
(3 nCK,
5ns)
Exit Precharge Power Down with DLL
frozen to commands requiring a lockedDLL
tXPDLL
tCKE
-
-
CKE minimum pulse width
2
Command pass disable delay
tCPDED
tPD
tCK
tCKE
(min)
9 * tREFI
Power Down Entry to Exit Timing
1
-
-
-
-
Timing of ACT command to Power Down entry
tACTPDEN
tPRPDEN
tRDPDEN
tWRPDEN
tCK
tCK
tCK
tCK
Timing of PRE or PREA command to
Power Down entry
1
RL + 4 + 1
WL + 4 +
Timing of RD/RDA command to Power Down entry
Timing of WR command to Power Down
entry (BL8OTF, BL8MRS, BC4OTF)
Timing of WRA command to Power
Down entry (BL8OTF, BL8MRS,BC4OTF)
Timing of WR command to Power Down entry
(BC4MRS)
(tWR / tCK
)
WL + 4 +
WR + 1
-
-
-
tWRAPDEN
tWRPDEN
tWRAPDEN
tCK
tCK
WL + 2 +
(tWR / tCK
)
Timing of WRA command to Power Down entry
(BC4MRS)
WL + 2 +
WR + 1
tCK
tCK
1
-
-
Timing of REF command to Power Down entry
Timing of MRS command to Power Down entry
ODT turn on Latency
tREFPDEN
tMRSPDEN
ODTLon
tMOD (min)
WL - 2 = CWL + AL - 2
WL - 2 = CWL + AL - 2
tCK
ODT turn off Latency
ODTLoff
Confidential
27
Rev. 3.0
Aug. /2014
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
