AS4C256M16D3
Table 17. Electrical Characteristics and Recommended A.C. Operating Conditions
(VDD = 1.5V 0.075V)
-12 BCN/BIN
Min. Max.
Symbol
Parameter
Unit
13.75
13.75
13.75
48.75
35
20
Internal read command to first data
ACT to internal read or write delay time
PRE command period
tAA
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCK
tCK
ps
tCK
ps
ps
-
tRCD
tRP
-
-
ACT to ACT or REF command period
ACTIVE to PRECHARGE command period
tRC
9 * tREFI
tRAS
CL=5, CWL=5
3.0
2.5
1.875
1.875
1.5
<3.3
<3.3
<2.5
<2.5
<1.875
<1.875
<1.5
-
CL=6, CWL=5
CL=7, CWL=6
CL=8, CWL=6
CL=9, CWL=7
CL=10, CWL=7
CL=11, CWL=8
Average clock period
tCK(avg)
1.5
1.25
8
Minimum Clock Cycle Time (DLL off mode)
Average clock HIGH pulse width
tCK
(DLL_OFF)
0.47
0.47
-
0.53
0.53
100
tCH(avg)
tCL(avg)
tDQSQ
Average Clock LOW pulse width
DQS, DQS# to DQ skew, per group, per access
DQ output hold time from DQS, DQS#
DQ low-impedance time from CK, CK#
DQ high impedance time from CK, CK#
Data setup time to DQS, DQS#
referenced to Vih(ac) / Vil(ac) levels
Data hold time from DQS, DQS#
referenced to Vih(dc) / Vil(dc) levels
0.38
-450
-
-
tQH
225
tLZ(DQ)
tHZ(DQ)
tDS(base)
225
10
45
-
-
AC150
ps
ps
tDH(base)
DC100
360
0.9
0.3
0.4
0.4
0.9
0.3
-
-
-
-
-
-
-
DQ and DM Input pulse width for each input
DQS,DQS# differential READ Preamble
DQS, DQS# differential READ Postamble
DQS, DQS# differential output high time
DQS, DQS# differential output low time
DQS, DQS# differential WRITE Preamble
DQS, DQS# differential WRITE Postamble
tDIPW
tRPRE
tRPST
tQSH
ps
tCK
tCK
tCK
tCK
tCK
tCK
tQSL
tWPRE
tWPST
DQS, DQS# rising edge output access
time from rising CK, CK#
DQS and DQS# low-impedance time
(Referenced from RL - 1)
DQS and DQS# high-impedance time
(Referenced from RL + BL/2)
-225
-450
-
225
225
225
tDQSCK
tLZ(DQS)
tHZ(DQS)
ps
ps
ps
0.45
0.45
-0.27
0.55
0.55
0.27
DQS, DQS# differential input low pulse width
DQS, DQS# differential input high pulse width
DQS, DQS# rising edge to CK, CK# rising edge
tDQSL
tDQSH
tDQSS
tCK
tCK
tCK
DQS, DQS# falling edge setup time to
CK, CK# rising edge
0.18
-
tDSS
tCK
DQS, DQS# falling edge hold time from
CK, CK# rising edge
0.18
512
-
-
-
tDSH
tDLLK
tRTP
tCK
tCK
DLL locking time
Internal READ Command to
max (4nCK,
7.5ns)
PRECHARGE Command delay
Delay from start of internal write
transaction to internal read command
max (4nCK,
7.5ns)
-
-
tWTR
tWR
15
WRITE recovery time
ns
Confidential
26
Rev. 3.0
Aug. /2014
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
