[AK4685]
Notes:
(1) The PDN pin should be set “L”Æ“H” after the all powers (TVDD, DVDD1/2/3, AVDD1/2/3 and PVDD) are
supplied. The AK4685 requires 150ns or longer “L” period for a reset. The AK4685 should be powered-up when the
PDN pin = “L”.
(2) Power-on the regulator, charge pump circuit, VCOM, HP-Amp and internal oscillator:
The PVEE pin becomes to the same voltage as PVEE within 8.0ms (max).
(3) The analog block of the ADC is initialized after exiting the power-down state.
(4) The analog block of the DAC is initialized after exiting the power-down state.
(5) The digital outputs corresponding to analog inputs, and the analog outputs corresponding to digital inputs have
group delay (GD).
(6) ADC output is “0” data at the power-down state.
(7) Click noise occurs at the end of initialization of the analog block. Mute the digital outputs externally if the click
noise influences a system application.
(8) A click noise occurs at the falling edge of PDN and at 512/fs after the rising edge(after charge-pump is power-on)
of PDN.
(9) Power-up of Headphone-Amp: PWHP bit = “0” Æ “1”
Headphone-Amp is in mute state and outputs ground level. Headphone-Amp power-up time is 27.7ms (max.).
(10) Headphone-Amp mute release: HPMTN pin = “L” Æ “H”
Headphone-Amp goes to the normal operation after the transition time. Headphone-Amp mute release time
depends on the setting of PTS1-0 and MOFF bits.
(11) Headphone-Amp mute: HPMTN pin = “H” Æ “L”
Headphone-Amp goes to mute state after the transition time set by PTS1-0 and MOFF bits.
(12) Headphone-Amp power-down: PWHPL/R bits = “1” Æ “0”
Headphone-Amp is powered-down immediately.
(13) PWDA2 bit = “1” Æ “0”
The PVEE pin becomes 0V according to the time constant of the capacitor at the PVEE pin and the internal
resistor. The internal resistor is 17.5kΩ (typ.).
(14) Mute the analog outputs externally if the click noise (8) influences a system application.
MS1106-E-00
2009/08
- 36 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
