[AK4685]
■ Reset Function
When RSTN bit = “0”, the ADC and DAC digital blocks are powered-down but the internal register are not initialized.
The analog outputs (LOUT+/-, ROUT+/- pins) go to VCOM voltage, the headphone outputs (HPL/R pins) go to ground
level (VSS5) and the SDTOB1/2 pins go to “L”. As some click noise occur, the analog outputs should be muted externally
if the click noise influences a system application. The Figure 18 shows the power-up sequence.
RSTN bit
4~5/fs (7)
1~2/fs
Internal
RSTN bit
(1)
516/fs
ADC Internal
State
Digital Block Power-down
Digital Block Power-down
Normal Operation
Init Cycle
Normal Operation
DAC Internal
State
Normal Operation
GD
Normal Operation
(2)
GD
ADC In
(Analog)
(3)
ADC Out
(Digital)
(4)
“0”data
DAC In
(Digital)
“0”data
(2)
GD
GD
(6)
(5)
(6)
DAC Out
(Analog)
Notes:
(1) The analog block of ADC is initialized after exiting the reset state.
(2) The digital outputs corresponding to the analog inputs, and the analog outputs corresponding to the digital inputs
have group delay (GD).
(3) ADC output is “0” data at power-down state.
(4) Click noise occurs when the internal RSTN bit becomes “1”. Mute the digital outputs externally if the click noise
influences a system application.
(5) When RSTN bit = “0”, the analog outputs go to 0V.
(6) A click noise occurs at 4∼5/fs after RSTN bit became “0”, and occurs at 1∼2/fs after RSTN bit becomes “1”.
(7) There is a delay about 4~5/fs from a writing “0” to the RSTN bit until the internal RSTN bit changes to “0”.
Figure 18. Reset Sequence Example
MS1106-E-00
2009/08
- 37 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
