[AK4685]
Power
MT2N pin
(1)
Normal Operation
Init Cycle
512/fs
DAC Internal State
(3)
ATT Level
Digital Attenuation
HDP State
-∞
HPMTN
Operation
Power
Down
HPMTN
Operation
Normal
Operation
Normal
Operation
MUTE
(4)
(2)
(5)
(6)
HDP OUT
(1) “L” time of 20ms or more is needed.
(2) The mute time of the headphone amplifier is 8.2ms (typ) and 14ms (max) when PTSA bit = “0” (at default PTS2-0
bits = “011”). PST2-0 bits setting does not effect this mute time. The mute time can be controlled by PTS2-0 bits
setting when PTSA bit = “1”.
A crick noise occurs when each power supply (TVDD, DVDD1/2/3, AVDD1/2/3 and PVDD) is off during mute
transition time. Power supplies should be provided longer than the transition time set by AMTS2-0 bits set.
(3) ATT_DATA x ATT transition time (Table 16). In case of MODE0 and ATS2-0 bits =“00H”, the transition time of
ATT value from FFH(0dB) to 00H(MUTE) is 1061/fs.
(4) Power down time of the headphone amplifier is controlled by AMTS2-0 bits. The AMTS2-0 bits setting value should
be shorter than PTS2-0 bits setting value.
(5) Headphone amplifier power-up: GND level is output when the headphone amplifier is muted. The headphone
amplifier power-up time is 27.7ms (max).
(6) The mute release time of the headphone amplifier is controlled by PTS2-0 bits or MOFF bit settings.
Figure 15. Mute Sequence Example (MT2N pin)
MS1106-E-00
2009/08
- 32 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
