[AK4685]
■ Power ON/OFF Sequence
The each block of the AK4685 is placed in power-down mode by bringing the PDN pin “L” and both digital filters are
reset at the same time. The PDN pin =“L” also reset the control registers to their default values. In power-down mode, the
DAC1/2 outputs go to VSS3/5 and the SDTOB1/2 pins go to “L”. The AK4685 should be powered-up when the PDN pin
= “L” to reset the internl registers.
In slave mode, after exiting reset at power-up or other situations, the ADC/DAC1/DAC2 starts operation on the rising
edge of LRCKB/A/C after MCB/MLCKA/C inputs. The ADC is in power-down mode until MCB is input, and the
DAC1/2 are in power-down mode until MLCKA/C or LRCKA/C is input.
The analog initialization cycle of ADC starts after exiting the power-down mode. Therefore, the output data, SDTOB1/2
becomes available after 522/fs cycles of LRCKB clock. In case of the DAC1/2, an analog initialization cycle starts after
exiting the power-down mode. The analog outputs are VSS3/5 during the initialization. Figure 17 shows the sequences of
the power-down and the power-up.
The ADC and DAC’s can be powered-down individually by PWAD and PWDA1/2 bits. These bits do not initialize the
internal register values. When PWAD bit = “0”, the SDTOB1/2 pins go to “L”. When PWDA1 bit = “0”, the analog
outputs (LOUT+/-, ROUT+/- pins) go to VCOM voltage. When PWDA2 bit = “0”, the headphone outptus (HPL/R pins)
go to VSS5 voltage. As some click noise occurs, the analog output should be muted externally if the click noise influences
a system application.
Power
(1)
PDN
PWDA2 bit
(2)
PVEE pin
0V
PVEE
0V
(3)
522/fs
(13)
ADCInternal
State
Init Cycle
Normal Operation
Normal Operation
Power-down
Power-down
512/fs
(4)
DAC Internal
State
Init Cycle
(5)
GD
GD
ADC In
(Analog)
ADC Out
(Digital)
“0”data (6)
“0”data
(7)
“0”data
“0”data
DAC In
(Digital)
(3)
GD
GD
(8)
(8)
(8)
DAC Out
(Analog)
Clock In
Don’t care
Don’t care
Mute ON
MCLK,LRCK,BICK
External
Mute
(14)
Mute ON
PWHP bit
HPMTN pin
0V
Normal
MUTE
MUTE
0V
HPL/HPR pins
(11) (12)
(9)
(10)
Figure 17. Power-up/down Sequence Example
MS1106-E-00
2009/08
- 35 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
