[AK4685]
2. WRITE Operations
Set R/W bit = “0” for the WRITE operation of the AK4685.
After receipt of the start condition and the first byte, the AK4685 generates an acknowledge, and awaits the second byte
(register address). The second byte consists of the address for control registers of AK4685. The format is MSB first, and
those most significant 3-bits are “Don’t care”.
*
*
*
A4
A3
A2
A1
A0
(*: Don’t care)
Figure 23. The Second Byte
After receipt of the second byte, the AK4685 generates an acknowledge, and awaits the third byte. Those data after the
second byte contain control data. The format is MSB first, 8bits.
D7
D6
D5
D4
D3
D2
D1
D0
Figure 24. Byte structure after the second byte
The AK4685 is capable of more than one byte write operation in one sequence.
After a receipt of the third byte, the AK4685 generates an acknowledge, and awaits the next data again. The master can
transmit more than one word instead of terminating the write cycle after the first data word is transferred. After the receipt
of each data, the internal 5bits address counter is incremented by one, and the next data is taken into next address
automatically. If the address exceeds 0CH prior to generating the stop condition, the address counter will “roll over” to
00H and the previous data will be overwritten.
S
S
T
O
P
T
A
R
T
Slave
Address
Register
Address(n)
Data(n)
Data(n+1)
Data(n+x)
S
P
SDA
A
C
K
A
C
K
A
C
K
A
C
K
Figure 25. WRITE Operation
MS1106-E-00
2009/08
- 40 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
