[AK4685]
■ Charge Pump Circuit
The internal charge pump circuit generates negative voltage (PVEE) from PVDD voltage for headphone amplifiers. The
internal charge pump starts operation when PWDA2 bit = “1”.
The power up time of charge pump circuit is maximum 8.0ms. When PWHP bits = “1”, the Headphone-Amp is
powered-up after the charge pump circuit is powered-up.
■ Headphone-Amp (HPL/HPR pins)
Power supply voltage for headphone amplifiers is applied from a regulator for positive power and a charge-pump for
negative power. The Regulator is driven by AVDD3 and the charge-pump is driven by PVDD. The PVEE pin outputs the
negative voltage generated by the internal charge pump circuit. The headphone amplifier output is single-ended and
centered on 0V (VSS5). Therefore, the capacitor for AC-coupling can be removed. The minimum load resistance is 32Ω.
When the DAC input signal level is 0dBFS, the output voltage is 1.21Vrms (= 31mW @ 32Ω via 6.8ohm resistor) at
HPGA4-0 bits = 0dB. The output level of headphone-amp can be controlled by HPGA4-0 bits. This volume setting is
common to L/R channels and can attenuate / gain the mixer output from +12dB to –50dB in 2dB step. When changing the
volume, pop noise occurs.
HPGA4-0 bits
GAIN (dB)
Step
1FH
1EH
:
+12
+10
:
1AH
19H
18H
17H
16H
:
+2
0
−2
−4
−6
:
(default)
2dB
2H
1H
0H
−46
−48
−50
Table 19. Headphone-Amp Volume Setting
When PWHP bit is “1”, the headphone-amps are powered-up. The headphone output is enabled when HPMTN bit is “1”
and muted when HPMTN bit is “0”. The mute ON/OFF time is set by PTS1-0 bits when MOFF bit is “0”.
MUTE ON/OFF Time
PTS2
PTS1
PTS0
typ.
max.
(reserved)
(reserved)
6.9ms
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
(reserved)
(reserved)
4.1ms
8.2ms
13.9ms
16.4ms
32.8ms
65.6ms
131.2ms
27.7ms
55.4ms
100.8ms
221.6ms
(default)
Table 20. Headphone-Amp Mute ON/OFF Transition Time
MS1106-E-00
2009/08
- 29 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
