[AK4685]
Soft transition Enable/Disable is controlled by MOFF bit. When this bit is “1”, soft transition is disabled and the
headphone is switched ON/OFF immediately. When soft transition is enabled, a register setting of the address 0BH
should be made in an interval more than soft transition time. Register writings are ignored if the same value is written to
these registers.
When PWHP bit is “0”, the headphone-amps are powered-down completely. At that time, the HPL and HPR pins go to
VSS5 voltage via the internal pulled-down resistor. The pulled-down resistor is 20Ω(typ) at HPZ bit = “0”, 50kΩ(typ) at
HPZ bit = “1”. The power-up time is 16.4ms (typ.) and 27.7ms (max.), and power up/down is executed immediately.
PWHP
HPZ
PWDA2
HPMTN
Mode
Power-down & Mute
N/A
HPL/R pin states
0
0
0
1
1
1
0
1
1
x
x
x
x
0
1
0
1
1
x
x
x
x
0
1
(default)
Pulled-down by 20Ω (typ)
N/A
Power-down
Pull-down by 50kΩ (typ)
N/A
Mute
Normal Operation
N/A
VSS5
Normal Operation
Table 21. Headphone Outputs Status (x: Don’t’ care)
■ Clock Stop Detection Function
When MCLKA, MCB and MCLKC external clocks are stopped, corresponding digital blocks become power-down
mode.
The power-down mode is released automatically and digital blocks return to normal operation when external clocks are
supplied again. An initialization cycle of 522/fs is taken before returning to normal operation when MCB clock is
stopped.
MS1106-E-00
2009/08
- 30 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
