[AK4671]
2. PCM I/F A Master Mode
Example:
Power Supply
PCM I/F A Format : Linear, Short Frame (ADC & DAC)
PLLBT Reference clock: SYNCB
SYNCB frequency: 1fs2
(1)
PDN pin
Sampling Frequency: 8kHz
(3)
(2)
PMVCM bit
(Addr:00H, D0)
4fs of
(1) Power Supply & PDN pin = “L” Æ “H”
PMPCM bit
(Addr:53H, D2)
(2) Addr:02H, Data:C0H
Addr:03H, Data:12H
Addr:54H, Data:00H
Addr:53H, Data:00H
Addr:55H, Data:00H
SYNCB pin
BICKB pin
Input
(4)
Internal Clock
(5)
(6)
(3) Addr:00H, Data:01H
(4) Addr:53H, Data:04H
SYNCA pin
BICKA pin
Output
Figure 123. Clock Set Up Sequence (2)
<Example>
(1) After Power Up, PDN pin = “L” Æ “H”. “L” time of 150ns or more is needed to reset the AK4671.
The AK4671 should be operated as the recommended power-up/down sequence shown in “System Design
(Grounding and Power Supply Decoupling)” to avoid pop noise at the receiver output, headphone output and
lineout output.
(2) BTCLK, LP, SDOD, FMTA1-0, LAWA1-0, BCKPA, MSBSA, PLLBT3-0 bits should be set during this
period.
(3) Power Up VCOM: PMVCM bit = “0” Æ “1”
VCOM should first be powered up before the other block operates.
(4) PLLBT starts after the PMPCM bit changes from “0” to “1” and PLLBT reference clock (SYNCB or BICKB
pin) is supplied. PLLBT lock time is 260ms(max.) when SYNCB is a PLLBT reference clock. And PLLBT
lock time is 40ms(max.) when BICKB is a PLLBT reference clock.
(5) Normal operation stats after that the PLLBT is locked.
(6) The invalid frequency is output from SYNCA and BICKA after PLLBT is locked.
MS0666-E-02
2010/06
- 158 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
