[AK4671]
■ Stop of Clock
Master clock can be stopped when ADC and DAC are not used.
1. PLL Master Mode
Example:
Audio I/F Format: MSB justified (ADC & DAC)
BICK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 11.2896MHz
Sampling Frequency: 44.1kHz
(1)
PMPLL bit
(Addr:02H, D0)
(1)
"1" or "0"
MCKO bit
(Addr:02H, D2)
(1) Addr:02H, Data:02H
(2)
External MCKI
Input
(2) Stop an external MCKI
Figure 117. Clock Stopping Sequence (1)
<Example>
(1) Power down PLL: PMPLL bit = “1” → “0”
Stop MCKO clock: MCKO bit = “1” → “0”
(2) Stop an external MCKI clock.
2. PLL Slave (MCKI pin)
Example
Audio I/F Format: MSB justified (ADC & DAC)
PLL Reference clock: MCKI
(1)
PMPLL bit
(Addr:02H, D0)
BICK frequency: 64fs
Sampling Frequency: 44.1kHz
(1)
MCKO bit
(Addr:02H, D2)
(1) Addr:02H, Data:00H
(2)
External MCKI
Input
(2) Stop the external clocks
Figure 118. Clock Stopping Sequence (2)
<Example>
(1) Power down PLL: PMPLL bit = “1” → “0”
Stop MCKO output: MCKO bit = “1” → “0”
(2) Stop the external master clock.
3. PLL Slave Mode (LRCK or BICK pin)
Example
Audio I/F Format: MSB justified (ADC & DAC)
PLL Reference clock: BICK
BICK frequency: 64fs
(1)
PMPLL bit
(Addr:02H, D0)
Sampling Frequency: 44.1kHz
(2)
External BICK
External LRCK
Input
Input
(1) Addr:02H, Data:00H
(2)
(2) Stop the external clocks
Figure 119. Clock Stopping Sequence (3)
<Example>
(1) Power down PLL: PMPLL bit = “1” → “0”
(2) Stop the external BICK and LRCK clocks
MS0666-E-02
2010/06
- 155 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
