[AK4671]
■ Stop of Clock
Master clock can be stopped when ADC and DAC are not used.
1. PCM I/F A Slave Mode
Example
PCM I/F A Format : Linear, Short Frame (ADC & DAC)
PLLBT Reference clock: SYNCA
SYNCA frequency: 1fs2
(1)
PMPCM bit
(Addr:53H, D2)
Sampling Frequency: 8kHz
(2)
External SYNCA
External BICKA
Input
Input
(1) Addr:53H, Data:00H
(2)
(2) Stop the external clocks
Figure 127. Clock Stopping Sequence (1)
<Example>
(1) Power down PLLBT: PMPCM bit = “1” → “0”
(2) Stop the external SYNCA and BICKA clocks
2. PCM I/F A Master Mode
(1)
PMPCM bit
(Addr:53H, D2)
(2)
Example
PCM I/F A Format : Linear, Short Frame (ADC & DAC)
PLLBT Reference clock: SYNCB
SYNCB frequency: 1fs2
External SYNCB
External BICKB
SYNCA
Input
(2)
Sampling Frequency: 8kHz
Input
Output
(1) Addr:53H, Data:00H
"H" or "L"
"H" or "L"
BICKA
Output
(2) Stop the external clocks
Figure 128. Clock Stopping Sequence (2)
< Example >
(1) Power down PLLBT: PMPCM bit = “1” → “0”
(2) Stop the external SYNCB and BICKB clocks. SYNCA and BICKA are fixed to “H” or “L”.
■ Power down
Power supply current can be shut down (typ. 20μA) by stopping clocks and setting PMVCM bit = “0” after all blocks
except for VCOM are powered-down. Power supply current can be also shut down (typ. 1μA) by stopping clocks and
setting the PDN pin = “L”. When the PDN pin = “L”, the registers are initialized.
MS0666-E-02
2010/06
- 162 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
