[AK4671]
■ Receiver-Amp Output
Example:
PCM I/F A: Slave Mode
PCM I/F A Format : Linear, Short Frame (ADC & DAC)
Sampling Frequency: 8kHz
Digital Volume Level: −8dB
RCV Volume Level: 0dB
5 band EQ: Enable
L1VL2-0 bits
101
100
01
(Addr:08H, D2-0)
(1)
SRMXR1-0 bits
(Addr:15H, D7-6)
(1) Addr:08H, Data:B4H
Addr:15H, Data:40H
Addr:0AH, Data:01H
Addr:0FH, Data:20H
00
DACR bit
(Addr:0AH, D0)
(10)
(2) Addr:18H, Data:0AH
(3) Addr:1BH, Data:28H
(4) Addr:0FH, Data:24H
RCV bit
(Addr:0FH, D5)
EQ bit
(Addr:18H, D3)
0
1
0
(2)
(9)
(5) Addr:53H, Data:06H
Addr:00H, Data:81H
Addr:0FH, Data:27H
OVR7-0 bits
(Addr:1BH, D7-0)
18H
28H
(3)
(6) Addr:0FH, Data:23H
Phone Call
LOPS1 bit
(Addr:0FH, D2)
(4)
(6)
(7)
(11)
PMSRB bit
(Addr:53H, D1)
(7) Addr:0FH, Data:27H
(8) Addr:53H, Data:04H
Addr:00H, Data:01H
Addr:0FH, Data:24H
PMDAR bit
(Addr:00H, D7)
(5)
(8)
PML/RO1 bits
(9) Addr:18H, Data:02H
(10) Addr:0AH, Data:00H
(11) Addr:0FH, Data:20H
(Addr:0FH, D1-0)
>1 ms
RCP pin
RCN pin
Normal Output
Figure 125. Receiver-Amp Output Sequence
(Phone Call Rx: SDTIA → PCM I/F A → SRC-B → EQ → DATT → DACR → RCP/RCN)
<Example>
At first, clocks should be supplied according to “Clock Set Up” sequence. Also, SRC-B, DAC and Receiver-Amp
should be powered-up in consideration of PLLBT lock time.
(1) Set up the path of “SDTIA Æ DAC Æ Receiver-Amp”: SRMXR1-0 bits = “00” Æ “01”, DACR bit = “0” Æ
“1”, RCV bit = “0” Æ “1”
Set up analog volume for Receiver-Amp (Addr: 08H, L1VL2-0 bits)
(2) Enable 5-band Equalizer: EQ bit = “0” Æ “1” (Boost amount is selected by Addr = 50H-52H.)
(3) Set up the output digital volume (Addr: 1BH)
When OVOLC bit is “1” (default), OVL7-0 bits set the volume of both channels. After DAC is powered-up,
the digital volume changes from default value (0dB) to the register setting value by the soft transition.
(4) Enter power-save mode of Receiver-Amp: LOPS1 bit = “0” Æ “1”
(5) Power-up SRC-B, DAC and Receiver-Amp: PMSRB bit = PMDAR = PMLO1 = PMRO1 bits = “0” → “1”
RCN pin rise up to VCOM voltage after PMLO1 and PMRO1 bits are changed to “1”.
(6) Exit power-save mode of Receiver-Amp: LOPS1 bit = “1” Æ “0”
LOPS1 bit should be set to “0” after PCN pin rise up. Receiver-Amp goes to normal operation by setting
LOPS1 bit to “0”.
(7) Enter power-save mode of Receiver-Amp: LOPS1 bit: “0” Æ “1”
(8) Power-down SRC-B, DAC and Receiver-Amp: PMSRB bit = PMDAR = PMLO1 = PMRO1 bits = “1” → “0”
Receiver-Amp becomes to power-down mode.
(9) Disable 5-band Equalizer: EQ bit = “1” Æ “0”
(10)Disable the path of “DAC Æ Receiver-Amp”: DACR bit = “1” Æ “0”
(11)Exit power-save mode of Receiver-Amp: LOPS1 bit = “1” Æ “0”
LOPS1 bit should be set to “0” after Receiver-Amp power-down.
MS0666-E-02
2010/06
- 160 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
