[AK4671]
■ Stereo Line Output
Example:
PLL, Master Mode
Audio I/F Format: MSB justified (ADC & DAC)
Sampling Frequency: 44.1kHz
OVOLC bit = “1”(default)
Digital Volume Level: −8dB
LINEOUT Volume Level: −3dB
FS3-0 bits
0000
1111
01
(Addr:01H, D7-4)
(1)
L3VL1-0 bits
10
(1) Addr:01H, Data:F4H
(Addr:11H, D7-D6)
(2)
(2) Addr:11H, Data:40H
Addr:1DH, Data:01H
Addr:15H, Data:05H
PFSEL bis
(Addr:1DH, D0)
Addr:0DH&0EH, Data:01H
PFMXL/R1-0 bits
0000
0101
28H
(Addr:15H, D3-0)
(3) Addr:1AH&1BH, Data:28H
(4) Addr:11H, Data:44H
DACSL/R bits
(Addr:0DH&0EH, D0)
(9)
(5) Addr:00H, Data:C1H
Addr:11H, Data:47H
OVL/R7-0 bits
18H
(Addr:1AH&1BH, D7-0)
(3)
(6) Addr:11H, Data:43H
Playback
LOPS3 bit
(Addr:11H, D2)
(4)
(6)
(7)
(10)
PMDAL/R bits
(Addr:00H, D7-6)
(7) Addr:11H, Data:47H
(5)
(8)
(8) Addr:00H, Data:01H
Addr:11H, Data:44H
PML/RO3 bits
(Addr:11H, D1-0)
>300 ms
>300 ms
(9) Addr:0DH&0E, Data:00H
(10) Addr:11H, Data:40H
LOUT3 pin
ROUT3 pin
Normal Output
Figure 116. Stereo Lineout Sequence
(Speaker Playback: SDTI → Audio I/F → SVOLA → DATT → DACL/R → LOUT3/ROUT3 → External SPK-Amp)
<Example>
At first, clocks should be supplied according to “Clock Set Up” sequence.
(1) Set up the sampling frequency (FS3-0 bits). When the AK4671 is PLL mode, DAC and Stereo Line-Amp
should be powered-up in consideration of PLL lock time after the sampling frequency is changed.
(2) Set up the path of “SDTI Æ DAC Æ Stereo Line-Amp”: PFSEL = “0” Æ “1”, PFMXL1-0 = PFMXR1-0 bits =
“0000” Æ “0101”, DACSL = DACSR bits = “0” Æ “1”
Set up analog volume for Stereo Line-Amp (Addr: 11H, L3VL1-0 bits)
(3) Set up the output digital volume (Addr: 1AH and 1BH)
When OVOLC bit is “1” (default), OVL7-0 bits set the volume of both channels. After DAC is powered-up,
the digital volume changes from default value (0dB) to the register setting value by the soft transition.
(4) Enter power-save mode of Stereo Line-Amp: LOPS3 bit = “0” Æ “1”
(5) Power-up DAC and Stereo Line-Amp: PMDAL = PMDAR = PMLO3 = PMRO3 bits = “0” → “1”
LOUT3 and ROUT3 pins rise up to VCOM voltage after PMLO3 and PMRO3 bits are changed to “1”. Rise
time is 300ms(max.) at C=1μF and AVDD=3.3V.
(6) Exit power-save mode of Stereo Line-Amp: LOPS3 bit = “1” Æ “0”
LOPS3 bit should be set to “0” after LOUT3 and ROUT3 pins rise up. Stereo Line-Amp goes to normal
operation by setting LOPS3 bit to “0”.
(7) Enter power-save mode of Stereo Line-Amp: LOPS3 bit: “0” Æ “1”
(8) Power-down DAC and Stereo Line-Amp: PMDAL = PMDAR = PMLO3 = PMRO3 bits = “1” → “0”
LOUT3 and ROUT3 pins fall down to VSS1. Fall time is 300ms(max.) at C=1μF and AVDD=3.3V.
(9) Disable the path of “DAC Æ Stereo Line-Amp”: DACSL = DACSR bits = “1” Æ “0”
(10)Exit power-save mode of Stereo Line-Amp: LOPS3 bit = “1” Æ “0”
LOPS3 bit should be set to “0” after LOUT3 and ROUT3 pins fall down.
MS0666-E-02
2010/06
- 154 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
