[AK4671]
CONTROL SEQUENCE (PCM)
■ Clock Set up
When ADC or DAC is powered-up, the clocks must be supplied.
1. PCM I/F A Slave Mode
Example:
PCM I/F A Format : Linear, Short Frame (ADC & DAC)
PLLBT Reference clock: SYNCA
SYNCA frequency: 1fs2
Sampling Frequency: 8kHz
Power Supply
4fs of
(1) Power Supply & PDN pin = “L” Æ “H”
(1)
PDN pin
(2)
(3)
PMVCM bit
(2) Addr:02H, Data:C0H
Addr:03H, Data:12H
Addr:54H, Data:00H
Addr:53H, Data:00H
Addr:55H, Data:00H
(Addr:00H, D0)
PMPCM bit
(Addr:53H, D2)
SYNCA pin
BICKA pin
Input
(4)
(3) Addr:00H, Data:01H
(4) Addr:53H, Data:04H
Internal Clock
(5)
Figure 122. Clock Set Up Sequence (1)
<Example>
(1) After Power Up, PDN pin = “L” Æ “H”. “L” time of 150ns or more is needed to reset the AK4671.
The AK4671 should be operated as the recommended power-up/down sequence shown in “System Design
(Grounding and Power Supply Decoupling)” to avoid pop noise at the receiver output, headphone output and
lineout output.
(2) BTCLK, LP, SDOD, FMTA1-0, LAWA1-0, BCKPA, MSBSA, PLLBT3-0 bits should be set during this
period.
(3) Power Up VCOM: PMVCM bit = “0” Æ “1”
VCOM should first be powered up before the other block operates.
(4) PLLBT starts after the PMPCM bit changes from “0” to “1” and PLLBT reference clock (SYNCA or BICKA
pin) is supplied. PLLBT lock time is 260ms(max.) when SYNCA is a PLLBT reference clock. And PLLBT
lock time is 40ms(max.) when BICKA is a PLLBT reference clock.
(5) Normal operation stats after that the PLLBT is locked.
MS0666-E-02
2010/06
- 157 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
