[AK4671]
5. EXT Master Mode
Example:
Audio I/F Format: MSB justified (ADC and DAC)
Input MCKI frequency: 256fs
Sampling Frequency: 44.1kHz
MCKO: Disable
(1) Power Supply & PDN pin = “L” Æ “H”
Power Supply
(1)
PDN pin
(2) MCKI input
(4)
PMVCM bit
(Addr:00H, D0)
(3) Addr:03H, Data:02H
Addr:01H, Data:00H
Addr:02H, Data:02H
(2)
(3)
MCKI pin
Input
M/S bit
(Addr:02H, D1)
BICK and LRCK output
(4) Addr:00H, Data:01H
LRCK pin
BICK pin
Output
Figure 113. Clock Set Up Sequence (5)
<Example>
(1) After Power Up, PDN pin = “L” Æ “H”. “L” time of 150ns or more is needed to reset the AK4671.
The AK4671 should be operated as the recommended power-up/down sequence shown in “System Design
(Grounding and Power Supply Decoupling)” to avoid pop noise at the receiver output, headphone output and
lineout output.
(2) MCKI should be input.
(3) After DIF1-0 and FS2-0 bits are set, M/S bit should be set to “1”. Then LRCK and BICK are output.
(4) Power Up VCOM: PMVCM bit = “0” Æ “1”
VCOM should first be powered up before the other block operates.
MS0666-E-02
2010/06
- 151 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
