[AK4679]
4. Read Operation (DLRDY bit = “1”)
4-1. Program RAM (PRAM) Read (during DSP Reset)
Field
Write data
Readout data
(1) COMMAND Code 0x38
(2) ADDRESS1
(3) ADDRESS2
(4) DATA1
0 0 0 0 A11 A10 A9 A8
A7 A6 A5 A4 A3 A2 A1 A0
0 0 0 0 D35 D34 D33 D32
D31~D24
(5) DATA2
(6) DATA3
D23~D16
(7) DATA4
D15~D8
(8) DATA5
D7~D0
Five bytes of data may be written continuously for each address.
4-2. Coefficient RAM (CRAM) Read (during DSP Reset)
Field
Write data
Readout data
(1) COMMAND Code 0x34
(2) ADDRESS1
(3) ADDRESS2
(4) DATA1
0 0 0 0 0 A10 A9 A8
A7 ~ A0
D19~D12
D11~D4
(5) DATA2
(6) DATA3
D3~D0 0 0 0 0
Three bytes of data may be written continuously for each address.
4-3. Offset REG (OFREG) Read (DSP Reset)
Field
Write data
Readout data
(1) COMMAND Code 0x32
(2) ADDRESS1
(3) ADDRESS2
(4) DATA1
0 0 0 0 0 0 0 0
0 0 0 A4 A3 A2 A1 A0
0 0 0 0 0 0 0 0
(5) DATA2
(6) DATA3
0 D14 D13 D12 D11 D10 D9 D8
D7~D0
Three bytes of data may be written continuously for each address.
5. Read Operation (DLRDY bit = “1” and RUN state)
5-1. Control Register Read (during DSP Reset and RUN)
Field
Write data
Readout data
Readout data
(1) COMMAND Code 0x40~0x47h
(2) DATA
D7~D0
5-2. System Power Supply Register Read (during DSP Reset and RUN)
Field Write data
(1) COMMAND Code 0x50~0x51
(2) DATA
D7~D0
5-3. Device Identification (during DSP Reset and RUN)
Field
Write data
Readout data
(1) COMMAND Code 0x60
(2) DATA
D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
1
1
0
0
1
1
9
MS1402-E-06
2013/02
- 195 -