[AK4679]
■ Command Format
DLRDY bit must be set “1” when the PRAM, CRAM, OFFREG will access on the sleep state.
1. Write Operation during DSP Reset
1-1. Program RAM (PRAM) Write (during DSP Reset)
Field
Write data
(1) COMMAND Code 0xB8
(2) ADDRESS1
(3) ADDRESS2
(4) DATA1
0 0 0 0 A11 A10 A9 A8
A7 A6 A5 A4 A3 A2 A1 A0
0 0 0 0 D35 D34 D33 D32
(5) DATA2
D31~D24
(6) DATA3
D23~D16
(7) DATA4
D15~D8
(8) DATA5
D7~D0
Five bytes of data may be written continuously for each address.
Note 79. SOPCFG bit selects SO output (Hi-z or Low) during CSN = “H”.
1-2. Coefficient RAM (CRAM) Write (during DSP Reset)
Field
Write data
(1) COMMAND Code 0xB4
(2) ADDRESS1
(3) ADDRESS2
(4) DATA1
0 0 0 0 0 A10 A9 A8
A7 A6 A5 A4 A3 A2 A1 A0
D19~D12
(5) DATA2
D11~D4
(6) DATA3
D3~D0 0 0 0 0
Two bytes of data may be written continuously for each address.
1-3. Offset REG (OFREG) Write (during DSP Rest)
Field Write data
(1) COMMAND Code 0xB2
(2) ADDRESS1
(3) ADDRESS2
(4) DATA1
0 0 0 0 0 0 0 0
0 0 0 A4 A3 A2 A1 A0
0 0 0 0 0 0 0 0
(5) DATA2
0 D14 D13 D12 D11 D10 D9 D8
(6) DATA3
D7~D0
Three bytes of data may be written continuously for each address.
2. Write Operation during DSP Reset (DLRDY bit = “1”) and RUN
2-1. Control Register Write (during DSP reset and RUN)
Field
(1) COMMAND Code 0xC0~0xC8
(2) DATA D7~D0
Write data
Note 85. Write operation may be limited depending on register settings. (C7: read only register)
2-2. System Power Supply Register Write (during DSP Reset and RUN)
Field
(1) COMMAND Code 0xD0~0xD1
(2) DATA D7~D0
Note 86. Write operation may be limited depending on register settings.
Write data
MS1402-E-06
2013/02
- 193 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
