[AK4679]
7. Timing
7-1. RAM Writing Timing during DSP Reset
Write to Program RAM (PRAM), Coefficient RAM (CRAM) and Offset REG (OFREG) during DSP reset in the order
of command code, address and data. The PRAM start address is fixed to 0h. When writing the data to consecutive
address locations, continue to input data only. PRAM address is incremented by 1 automatically.
DSPRSTN bit = “0”
CSN
DLRDY bit = “1”
SCLK
don’t care
(L/H)
don’t care
(L/H)
Command
Address
DATA
DATA
DATA
DATA
DATA
SI
Address[n]
Address[n+1]
RDY = “H”
Figure 138. Writing to RAM at Consecutive Address Locations
When writing data at specified address locations, set the CSN pin to “L” from “H” and then input command code, address
and data in this order.
DSPRSTN bit = “0”
CSN
DLRDY bit
SCLK
don’tcare
(L/H)
don’tcare
(L/H)
don’tcare
(L/H)
Command Address DATA
Command Address DATA
SI
RDY = “H”
Figure 139. Writing to RAM at specified Address Locations
MS1402-E-06
2013/02
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AKM [ ASAHI KASEI MICROSYSTEMS ]
