[AK4679]
■ Write
Command
Code
0x80~0x8F
Address
16bit
Data Length Description
24bit×n
Write preparation to CRAM during RUN.
Command code BIT3~BIT0 bits determines the amount of write operation.
(0x80 # of write: 1, 0x81 # of write: 2, ----, 0x8F # of write: 16) If the actual
amount of write operations exceeds the defined amount, that data will be
ignored.
0x90~0x9F
16bit
24bit×n
Write preparation to OFREG during RUN
Command code BIT3~BIT0 bits determines the amount of write operation.
(0x90 # of write: 1, 0x91 # of write: 2, ----, 0x9F # of write: 16) If the actual
amount of write operations exceeds the defined amount, that data will be
ignored.
0xA2
0xA4
0xB2
0xB4
0xB8
16bit
16bit
16bit
16bit
16bit
None
None
None
None
24bit×n
24bit×n
40bit×n
8bit
Write operation to OFREG during RUN. 0 address should be written.
Write operation to CRAM during RUN. 0 address should be written.
Write operation to OFREG during DSP reset
Write operation to CRAM during DSP reset
Write operation to PRAM during DSP reset
0xC0~0xC8
0xD0~0xD
1
Write operation to Register 0h~8h (except 7h)
System Power Supply Registers 0h~1h Write
8bit
0xF2
0xF4
None
None
16bit
8bit
CRC Write
Write operation of DSP JX code
Data length is defined by the command code which specifies the area to be accessed. When accessing RAM, data may be
read from sequential address locations by reading data continuously. Writing other than the above-mentioned command
code is prohibited.
Table 132. List of Usable Command Codes in Write Sequence
■ Read
Command
Code
Address
Data
Length
Description
0x24
0x32
0x34
16bit
16bit
16bit
16bit
None
None
None
None
None
None
24bit×n
CRAM/OFREG Write preparation data Read during RUN
Read operation form OFREG during DSP reset
Read operation from CRAM during DSP reset
Read operation from PRAM during DSP reset
Read operation from Register 0h~8h
Read operation from System Power Supply Register 0h~1h
Device Identification
DSP Error Status Read
24bit×n
24bit×n
40bit×n
8bit
8bit
8bit
8bit
16bit
32bit
0x38
0x40~0x48
0x50~0x 51
0x60
0x70
0x72
0x76
CRC result Read
Read operation from MIR1
28-bit is upper-bit justified. Lower 4-bits are for validity flags.
Read operation from MIR2
28-bit is upper-bit justified. Lower 4-bits are for validity flags.
Read operation from MIR3
28-bit is upper-bit justified. Lower 4-bits are for validity flags.
Read operation from MIR4
0x78
0x7A
0x7C
None
None
None
32bit
32bit
32bit
28-bit is upper-bit justified. Lower 4-bits are for validity flags.
Reading other than the above-mentioned command code is prohibited.
Table 133. List of Usable Command Codes in Read Sequence
MS1402-E-06
2013/02
- 192 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
