[AK4679]
CONT4: DSP Setting 2
Register
Address
Register Name
CONT4
R/W
D7
LPDO4
R/W
0
D6
LPDO3
R/W
0
D5
LPDO2
R/W
0
D4
LPDO1
R/W
0
D3
SELDO4
R/W
D2
SELDO3
R/W
D1
PT2N
R/W
0
D0
SELPT
R/W
0
W
R
C4h
44h
Default
0
0
LPDO4: SDOUT4 Signal Select (Figure 109) Valid when OUT4N bit = “0”
0: SDIN3 to SDOUT4 (default)
1: DSP DOUT4 to SDOUT4 pin
LPDO3: SDOUT3 Signal Select (Figure 109) Valid when OUT3N bit = “0”
0: SDIN4 to SDOUT3 (default)
1: DSP DOUT3 to SDOUT3 pin
LPDO2: SDOUT2 Signal Select (Figure 109) Valid when OUT2N bit = “0”
0: SDIN1 to SDOUT2 (default)
1: DSP DOUT2 to SDOUT2 pin
LPDO1: SDOUT1 Signal Select (Figure 109) Valid when OUT1N bit = “0”
0: SDIN2 pin to SDOUT1 pin (default)
1: DSP DOUT1 to SDOUT1 pin
SELDO4: SDOUT4/GP1 pin Signal Select (Table 131)
0: DSP DOUT4 Output (default)
1: DSP GP Output 1
SELDO3: SDOUT3/GP0 Signal Select (Table 130)
0: DSP DOUT3 Output (default)
1: DSP GP Output 1
PT2N: Port#2 Output Enable (Figure 108)
0: Enable (default)
1: Disable (BCLK2 and SYNC2 pin output Low level)
SELPT: Port Select of Port #2 Output (Figure 108)
0: Port#1 (SYNC1, BCLK1) (default)
SYNC3/JX1 and BCLK3/JX0 pins can be used as JX1 and JX0 pins respectively.
1: Port#3 (SYNC3, BCLK3)
MS1402-E-06
2013/02
- 188 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
